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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 24/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each XV1 to XV6 output signal. Table 13 summarizes the
registers available for generating each of the 10 vertical pattern
groups. The start polarity (VPOL) determines the starting
polarity of the vertical sequence and can be programmed high
or low for each XV1 to XV6 output. The first, second, and third
toggle positions (XVTOG1, XVTOG2, and XVTOG3) are the
p
f
Rev. A | Page 24 of 96
ixel locations within the line where the pulse transitions. A
ourth toggle position (XVTOG4) is also available for vertical
pattern groups 8 and 9. All toggle positions are 12-bit values,
allowing their placement anywhere in the horizontal line. A
Table 13. Vertical Pattern Group Registers
Register
Length Range
XVPOL
1 b
High/Low
XVTOG1
12 b
0 to 4096 Pixel Location
XVTOG2
12 b
0 to 4096 Pixel Location
XVTOG3
12 b
0 to 4096 Pixel Location
XVTOG4
12 b
0 to 4096 Pixel Location
the
ces
he
llows the AD9925 to remain back-
ward-compatible with the AD9995 register settings while still
providing additional flexibility with XV7 and XV8 for new CCDs.
Description
Starting Polarity of Each XV Output
First To
ggle Position within Line
Second To
ggle Position within
Third Toggle Position within Line for Each XV Output
Fourth Toggle Po
XV7 and XV8 Vertical Pattern Groups
Total Length of Each Vertical Pattern Group
Holds the XV Outputs at Their Current Levels (Static DC)
Resumes Operation of the XV Outputs to Finish Their Pattern
Holds the XV Outputs at Their Current Levels (Static DC)
Resumes Operation of the XV Outputs to Finish Their Pattern
separate register, VPATSTART, specifies the start position of
vertical pattern groups within the line (see the Vertical Sequen
(VSEQ) section). The VPATLEN register designates the total
length of the vertical pattern group, which determines the number
of pixels between each of the pattern repetitions when repetitions
are used (see the Vertical Sequences (VSEQ) section).
Additional VPAT groups are provided in Register Bank 3 for t
XV7 and XV8 outputs. This a
for Each XV Output
Line for Each XV Output
rtical Pattern Groups 8 and 9 and Also in
VPATLEN
FREEZE1
RESUME1 12 b
FREEZE2
RESUME2 12 b
12 b
12 b
0 to 4096 Pixels
0 to 4096 Pixel Location
0 to 4096 Pixel Location
0 to 4096 Pixel Location
0 to 4096 Pixel Location
sition, Only Available in Ve
12 b
HD
XV1
PROGRAMMABLE SETTINGS FOR EACH VERTICAL PATTERN:
1. START POLARITY.
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION (THIRD TOGGLE POSITION ALSO AVAILABLE,
FOURTH TOGGLE POSITION AVAILABLE FOR VERTICAL PATTERN GROUPS 8 AND 9).
4. TOTAL PATTERN LENGTH FOR ALL XV OUTPUTS.
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS
4
1
2
3
XV2
1
2
3
XV6
1
2
3
0
Figure 31. Vertical Pattern Group Programmability
相關(guān)PDF資料 |
PDF描述 |
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| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9927 | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9925KBCZ | 制造商:Analog Devices 功能描述:12 BIT, 36 MSPS CCD SIGNAL PROCESSOR W/VERTICAL DRIVER - Bulk |
| AD9926BBCZ | 制造商:Analog Devices 功能描述: |
| AD9926BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9927 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 1.8V/3V 128-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC 14BIT CCD SIGNAL PROCESSOR SMD |
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