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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 33/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
Table 17. SG Pattern Registers (Also See Field Registers in Table 15)
Register
Length
SGPOL
1 b
SGTOG1
12 b
SGTOG2
12 b
SGMASK_OVR
6 b
SGMASKOVR_EN
1 b
Rev. A | Page 33 of 96
Range
High/Low
0 to 4095 Pixel Location
0 to 4095 Pixel Location
Six Individual Bits
Disable/Enable
Description
Sensor Gate Starting Polarity for SG Pattern 0 to 3
First Toggle Position for SG Pattern 0 to 3
Second Toggle Position for SG Pattern 0 to 3
SG Masking, Overrides the Values in the Field Registers
1: Enables SGMASK Fast Update
VD
HD
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1. START POLARITY OF PULSE.
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION.
4. ACTIVE LINE FOR XSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).
XSG PATTERNS
4
1
2
3
0
Figure 42. Vertical Sensor Ga
r to
e-
s
, rather than having to write in all the vertical
mode is changed
timing information with each camera mode change.
ds
a
hese three bits. The remaining register bits are
divided into 3-bit sections to select which of the six fields ar
used and in which order. Up to seven fields may be used in a
single MODE write. The AD9925 will start with the field timin
specified by the first field bits, and on the next VD it will switch
to the timing specified by the second field bits, and so on.
e
g
.
until a new write to the MODE register occurs.
This will continue
Figure 43 shows examples of the MODE regis
different field configurations.
ter settings for
Table 18. MODE Register Data Bit Breakdown (D23 = MSB)
D23 D22 D21
D20 D19 D18
3 D12
D11 D10 D9
D8 D7 D6
D5 D4 D3
D2 D1 D0
te Pulse Placement
which field timing would be active depending on how the camer
was being used. Table 18 shows how the MODE register data
bits are used. The three MSBs, D23 to D21, are used to specify
how many total fields will be used. Any value from 1 to 7 can be
selected using t
D17 D16 D15
D14 D1
MODE Register
The MODE register is a single register that selects the field timing
of the AD9925. Typically, all the field, vertical sequence, and ver-
tical pattern group information is programmed into the AD9925
at startup. During operation, the MODE register allows the use
select any combination of field timing to meet the current requir
ments of the system. The advantage of using the MODE register in
conjunction with preprogrammed timing is that it greatly reduce
the system programming requirements during camera operation.
Only a few register writes are required when the camera operating
A basic still camera application might require five different fiel
of vertical timing: one for draft mode operation, one for auto-
focusing, and three for still image readout. All of the register
timing information for the five fields would be loaded at startup.
Then, during camera operation, the MODE register would select
After completing the total number of fields specified in Bits D23
to D21, the AD9925 will repeat by starting at the first field again
Total Number of
Fields to Use
1 = First Field Only 0 = Field 0
7 = All 7 Fields
0 = Invalid
Seventh Field
Sixth Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
Fifth Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
Fourth Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
Third Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
Second Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
First Field
0 = Field 0
5 = Field 5
6, 7 = Invalid
5 = Field 5
6, 7 = Invalid
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