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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 60/96頁 |
| 文件大小： | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
Register Address BANK 1, BANK
The AD99 5 address space is d vided into three
ter b
eferr
Regi
nk 3
divid
gister B
9995 re
ters for
AFE, m
ti
tions. Register Bank 2 contains all of the
vertical pattern groups, vertical sequences, and fi
Rev. A | Page 60 of 96
2, and BANK 3
2
dif
anks, r
ster Ba
ed. Re
ed to as Register
. Figure 76 illust
ank 1 and Ba
gisters. Regi
iscellaneous
nk 1, Register B
s how the three
re backward
Bank 1 contain
ctions, VD/HD
fun
le
s-
with the AD
the
ters,
ming core, CLPOB masking, VSG patterns, and shutter func-
information for the
eld i
ster Ba
functi
contains new reg
ty. These additio
Ds that requir
wer CC
r accessing
outputs allow th
-phases of verti
e 8
5 to
support ne
writ
the AD9925, A
k is being writ
ritten. To wri
o Bank 3, a da
write t
0x7F is used to
. To write to
Bank 2, a data
alue of 2 is writ
which addr
data value
ten. To
writ
Note that Register Bank 1 contains many unused addresses.
s between Addr 0x00 and Addr 0x7F are
Undefined addresse
considered Don’t Cares, and it is acceptable if
are filled in with all 0s during a continuous
tion. However, the undefin
written to, or the AD9925
tions are the FG_TRIG
these addresses
register write opera-
ed addresses above 0x7F must not be
may not operate properly. The excep-
registers 0xE7, 0xEB, and 0xF2 through
0xF6, which may be written as specified on Page 43.
Default values for Register Bank 2 and Bank 3 are undefined after
ate values should be written into these regis-
power-up. Appropri
ter banks to ensure proper operation. In ap
XV7 and XV8 signals are not used, the
still be programmed with
able behavior in the V-dri
plications where the
Bank 3 registers should
known values to prevent unpredict-
ver circuit.
ferent regis-
ank 2, and
banks are
compatib
s the regi
parame
Ba
rate
nk 2 a
ster
nformation.
Regi
XV8
nk 3
onali
isters fo
nal
the XV7 and
e AD992
cal clocking.
When
ing to
ess ban
of 0 is w
ddr
ten to
te to
ta v
specify
Bank 1, a
value of 1 is
ten.
AFE REGISTERS
SWITCH TO
REGISTER BANK 2, BANK 3
REGISTER BANK 1
ADDR 0x00
ADDR
MISCELLANEOUS REGISTERS
VD/HD REGISTERS
TIMING CORE REGISTERS
CLPOB MASK REGISTERS
VSG PATTERN REGISTERS
SHUTTER REGISTERS
ADDR
ADDR 0x20
ADDR 0x30
ADDR 0x40
ADDR 0x50
ADDR 0x60
0x7F
0x10
VPAT0 TO VPAT9 REGISTERS
FOR
V6 SIGNALS
XV1 TO X
SWI
REGISTER B
REGISTE
ADDR 0x00
VSEQ0 TO VSEQ9 REGISTERS
FOR
V6 SIGNALS
XV1 TO X
LD 0 TO FI
ADDR 0x7F
ADDR 0x80
ADD
ADD
ADDR 0x7E
ADD
W
ESS 0x7F
ADDR
ADDR 0x8F
TCH TO
ANK 1, BANK 3
R BANK 2
FIE
R 0xFF
ELD 5 REGISTERS
R 0xD0
R 0xCF
RITE TO ADDR
TO SWITCH REGISTER BANKS
0xFF
INVALID, DO NOT ACCESS
VPAT0 TO VPAT9 REGISTERS
FOR
XV7, XV8 SIGNALS
VSEQ0 TO VSEQ9 REGISTERS
FOR
XV7, XV8 SIGNALS
ADDR 0x77
ADDR 0x50
F
ADDR 0x4F
ADDR 0x7F
REGISTER BANK 3
ADDR 0x00
ADDR 0xF
INVALID, DO NOT ACCESS
0
SWITCH TO
REGISTER BANK 2, BANK 3
Figure 76.
Regi
Layout of Internal
ster Bank 1, Bank 2, and Bank 3
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