參數(shù)資料
型號(hào): AD9925BBCZRL
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝: 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù): 22/96頁(yè)
文件大?。?/td> 1447K
代理商: AD9925BBCZRL
AD9925
Rev. A | Page 22 of 96
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES
0
V
H
Figure 28. Example CCD Configuration
VERTICAL SHIFT
VERT SHIFT
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
OPTICAL BLACK
DUMMY
EFFECTIVE PIXELS
OB
OPTICAL BLACK
HD
0
Figure 29. Horizontal Sequence Example
VERTICAL TIMING GENERATION
The AD9925 provides a very flexible solution for generating
vertical CCD timing and can support multiple CCDs and dif-
ferent system architectures. The vertical transfer clocks XV1 to
XV8 are used to shift each line of pixels into the
ut register of the CCD. The AD9925 allows these outputs to be
individually programmed into various readout configurations,
sing a 4-step process.
u
Figure 30 shows an overview of how the vertical timing is gen-
erated in four steps. First, the individual pulse patterns for XV1
to XV8 are created by using the vertical pattern group registers.
Second, the vertical pattern groups are used to build the
sequences, where additional information is added. Third, the
readout for an entire field is constructed by dividing the field
into different regions and then assigning a sequence to ea
can contain up to seven different regions to
accommodate the different steps of the readout, such as high
speed line shifts and unique vertical line transfers. Up to six
different fields may be created. Finally, the MODE register al-
lows the different fields to be combined into any order for vari-
ous readout configurations.
horizontal out-
region. Each field
p
ch
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