參數(shù)資料
型號(hào)： AD9925BBCZRL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 62/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925BBCZRL
AD9925
COMPLETE LISTING FO
All r
s are V
Rev. A | Page 62 of 96
R REGISTER BANK 1
ight gray cells
egister
D updated, except where noted. L
= SCK
Table 37. AFE Register Map
ddress Data Bit Content
A
00
[11:0]
01
[9:0]
02
[7:0]
03
[11:0]
Default Value
7
0
80
4
Register Name
OPRMODE
VGAGAIN
CLAMPLEVEL
CTLMODE
Register Description
AFE Operation Modes (See Table 45 for detail)
VGA Gain
O
ptical Black Clamp Leve
AFE Control Modes (See Table 46 for detail)
updated, and dark gray cells = SG line updated.
Table 38. Miscellaneous Regist
s
Addres
Data B
0A
[17:0]
0B
[17:0]
0C
[17:0]
0D
[17:0]
10
[0]
it Content
lt Value
Register Descri
Polarities for Output Signals during Standby 1 Mode.
Polarities for Output Signals during Standby 2 Mode.
Po
larities for Output Signals during Standby 3 M
Polarities for Output Signals When OUTCONTROL = 0.
Software Reset. 1: Reset all registers to default, then self clear back
to 0.
O
utput Control. 0: Make all outputs dc
Configures Pin 52 as a SYNC Input (= 1) or CLPOB/PBLK Output (= 0).
SYNC Active Polarity (0: Active Low).
Suspend Clocks during SYNC Active (1: Suspend).
Timing Core Reset Bar. 0: Reset TG Core, 1: Resume Operation.
CL
O Oscillator Power-Down (0: Oscillator Is Po
er Map
Defau
3FF8
3FF8
0
3FF8
0
Register Name
STBY1POL
STBY2POL
STBY3POL
OCONTPOL
SW_RST
ption
ode.
11
12
13
14
15
16
[0]
[0]
[0]
[0]
[0]
[0]
0
1
0
0
0
1
OUTCONTROL
SYNCENABLE
SYNCPOL
SYNCSUSPEND
TGCORE_RSTB
OSC_PWRDOW
N
UNUSED
TEST
UPDATE
PREVENTUP-
DATE
MODE
UNUSED
OUTPUTPBLK
inactive.
wered Down).
17
18
19
1A
[0]
[11:0]
[0]
0
0
0
Set to 0.
Internal Use Only. Must be set to 0.
Se
rial Update. Line (HD) in the field to update
Pr
events the update of the VD updated registers. 1: Prevent Update.
VD updated registers.
1B
1C
1D
[23:0]
[0]
0
0
MODE Register.
Set to 0.
Assigns Output for Pin 52 When Configured as Output.
0: CLPOB, 1: PBLK.
1: Enable DVC Mode. VD counter will reset every 2 fields, instead of
every field. VDLEN register should be programmed to the total num-
ber of lines contained in 2 fields, e.g., VDLEN = 525 lines will results
in 262.5 lines in each field.
1: Invert the DCLK Output.
Set to 0.
Selects FG_TRIG Signal to VSUB Pin (See Page 43).
Set to 0.
H3HBLKOFF, Set to 1 to Enable H3/H4 Outputs during HBLK (See
Page 19).
Set to 0.
Combines FG_TRIG and VSUB Signals (See Page 43).
FG_TRIG Signal Enable (See Page 43).
FG_TRIG Start Polarity.
FG_TRIG First Toggle Position, Line Location.
FG_TRIG First Toggle Position, Pixel Location.
FG_TRIG Second Toggle Position, Line Location.
FG_TRIG Second Toggle Position, Pixel Location.
1E
[0]
0
DVCMODE
1F
E7
[0]
[2:0]
[3]
[5:4]
[6]
[7]
[8]
[3:0]
[0]
[11:0]
[12:0]
[11:0]
[12:0]
0
0
INVERT_DCLK
SHUT_EXTRA
EB
F2
F3
F4
F5
F6
0
0
0
0
0
0
FG_TRIGEN
FG_TRIGPOL
FG_TRIGLIN1
FG_TRIGPIX1
FG_TRIGLIN2
FG_TRIGPIX2
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