參數(shù)資料
型號(hào)： AD9925BBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 19/96頁(yè)
文件大小： 1447K
代理商： AD9925BBCZRL
AD9925
to specify six individual lines within th
contain an
e CLPOB ulse. CLP
mode of oper ion.
Rev. A | Page 19 of 96
e field. These lines will not
MASKTYPE is set l
activ
p
at
SK re
e CLPMAS
. Th
cif
ue
lines
grammed to specify the starting and ending lines in the f
the CLPOB patterns will be ignored. There are three sets
es,
ng up
M
E
created. CLP ASKTYP is set high for this mode of o eration.
ar
p
m
y
regi
ays
B ma
of
ers
be set to the maximum value of 0xFFF (default value).
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 24 is similar
to CLPOB and PBLK, but there is no start p
the toggle positions are used to designate the start and the stop
olarity control. Only
itionally, there is a polarity
designates the polarity of the horizontal
g the blanking period. Setting
2 = H4 = High
he CLPOB
ach vertical
e used with
e H3/H4 signals
to remain active during HBLK. To do this, set register Bit D6 in
Addr 0xE7 equal to 1. This feature is usef
used to drive the HL (last horizontal gate) input of the CCD.
ul if the H3 output is
iption
ow for this
Second, th
of adjacent
e CLPMA
gisters can be used to spe
K start and end line val
y blocks
s are pro-
ield, where
of start
positions of the blanking period. Add
control HBLKMASK that
clock signals H1 to H4 durin
HBLKMASK high will set H1 = H3 = Low and H
during the blanking, as shown in Figure 25. As with t
and PBLK signals, HBLK registers are available in e
and end valu
allowi
to three CLPOB masking eas to be
The CLPOB asking
sequence; the are alw
To disable th CLPO
sters are not specific to a ce ain vertical
active for any existing field timing.
sking feature, these regist
sequence, which allow different blanking signals to b
different vertical timing sequences.
should
One additional feature is the ability to enable th
Table 10. CLPOB and PBLK Pattern Registers
Register
Length Range
SPOL
1 b
TOG1
12 b
TOG2
12 b
CLPOBMASK
12 b
Descr
Starting Polarity of CLPOB/PBLK for Vertical Sequence 0 to 9.
First Toggle Position within Line for Vertical Sequence 0 to 9.
Second Toggle Position within Line for Vertical Sequence 0 to 9.
CLPOBMASK0 thr
CLPOB pulse to be
three ranges of ad
jacent lines, rather than six individual lines.
When set low (default), the CLPOBMASK registers select individual lines in the field
to disable the CLPOB pulse. When set high, the range masking is enabled, allowing
up to three blocks of adjacent lines to have the CLPOB signal masked. CLPOB-
MASK0 and CLPOBMASK1 are the start/end of the first block of lines, CLPOBMASK2
and CLPOBMASK3 are the start/end of the second block, and CLPOBMASK4 and
CLPOBMASK5 are the start/end of the third block.
High/Low
0 to 4095 Pixel Location
0 to 4095 Pixel Location
0 to 4095 Line Location
e
ed to specify
ough CLPOBMASK5 specify six individual lines in the field for th
temporarily disabled. These registers can also be us
CLPMASKTYPE
1 b
High/Low
3
2
1
HD
CLPOB
PBLK
NOTES
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
2. FIRST TOGGLE POSITION.
3. SECOND TOGGLE POSITION.
ACTIVE
ACTIVE
0
Figure 23. Clamp and Preblank Pulse Placement
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