參數(shù)資料
型號(hào)： AD9925BBCZRL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 59/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925BBCZRL
AD9925
SERIAL INTERFACE TIMING
All of the internal registers of the AD9925 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both t
word are written starting with t e LSB. To write
a 32
eration i
man
ters are f
writ
each r
bits
hen the
are D
fi
bits are written, the register will not be up
Rev. A | Page 59 of 96
he 8-bit address and 24-bit data-
s required, as
own in Figure 7
ewer than 24
wide, all 24 bi
egister. For exa
, if the registe
upper 14 bits
on’t Cares an
lled with 0s during the serial write operation. If fewer than 24
to
-bit op
y regis
ten for
wide, t
dated with new data.
Figure 75 shows a more efficient way to write to the registers,
using the AD9925’s address automatic increment capability.
Using this method, the lowest desired address is
written first,
followed by multiple 24-bit data-words. Each new 24-bit data-
ally be written to the next highest register
word will automatic
address. By eliminating the need to write ea
gister loading is achieved. Continuo
faster re
may be used starting wi
to write to as few as two registers or to as ma
register space.
ch 8-bit address,
us write operations
th any register location and may be used
ny as the entire
each register,
4. Although
ts must be
r is only 10
d may be
sh
bits
mple
SDATA
A0
A1
A4
A5
D1
D
A2
A6
A7
D0
2
D3
D21
D22
D23
SCK
SL
A3
t
LS
t
DS
8-BIT ADDRESS
1
2
4
5
6
9
10
24-BIT DATA
32
11
12
30
31
3
7
8
0
t
LH
t
DH
NOTES
1. SDATA BITS
2. ALL 32 BITS
3. IF THE REGISTER LENGTH IS < 24 BIT
ALU
RE
LATCHED ON SCK
T BE WRITTEN: 8 BI
MUS
AY
2
BIT
4. NEW DATA V
PARTICULAR
ES ARE UPDATED IN
GISTER WRITTEN TO
IST
UP
74. Serial Wr
on
ARE
RISING EDGES. SCK M
TS FOR ADDRESS AND
S, THEN DON’T CARE
IDLE HIGH OR LOW IN BETWEEN WRITE OPERATIONS.
4 BITS FOR DATA.
S MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
THE SPECIFIED REG
. SEE THE REGISTER
ER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
DATES SECTION FOR MORE INFORMATION.
Figure
ite Operati
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D22
D23
SCK
SL
A3
NOTES
1.
MULTIPLE SEQUE
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN,
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4.
SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN L
L REGISTERS MAY B
UOU
NTIA
E LOADED CONTIN
SLY.
FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
OADED.
D0
D1
D22
D23
D0
DATA FOR S
EGISTER A
R
DATA FOR NEXT
REGISTER ADDRESS
1
2
3
4
5
6
7
0
TARTING
DDRESS
D2
D1
32
31
34
33
56
55
58
57
59
8
9
10
erial Write O
Figure 75. Continuous S
peration
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