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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 51/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
POWER-UP AND SYNCHRONIZATION
Vertical Driver Power Supply Sequencing
The recommended Power-Up and Power-Down sequences are
shown in Figure 65 and Figure 66, respectively. As shown, the
VM1 and VM2 voltage levels should never exceed the VH1 and
VH2 voltage levels during power-up or power-down. Excessive
current will result if this requirement is not met due to a PN
junction diode turning on between the VM1/VM2 and VH
supply pins.
Rev. A | Page 51 of 96
0V
1
2
VH1 = VH2 = 12.0V TO 15.0V
DD = TCVDD = AVDD = 3.0V
VM1 = VM2 = –1.0V TO –0.5V
VL = –7.5V
SAME TIME AS VM AND VH; LATER OR EARLIER IS OK, BUT NOT BEFORE VDD REACHES 3.0V.
0
VDVDD = DVDD = DRVDD = HVDD = RGV
Figure 65. Power-Up Sequence
0V
VH1 = VH2
VDVDD = DVDD = DRVDD = HVDD = RGVDD = TCVDD = AVDD = 3V
2
1
VM1 = VM2
VL
SAME TIME AS VM AND VH OR EARLIER, BUT NOT AFTER VDD.
0
n Sequence
Figure 66. Power-Dow
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| AD9925KBCZ | 制造商:Analog Devices 功能描述:12 BIT, 36 MSPS CCD SIGNAL PROCESSOR W/VERTICAL DRIVER - Bulk |
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