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參數(shù)資料
| 型號： | AD9925BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA96 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96 |
| 文件頁數(shù)： | 21/96頁 |
| 文件大小： | 1447K |
| 代理商： | AD9925BBCZRL |
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AD9925
Rev. A | Page 21 of 96
HBLK
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS
H1/H3
H2/H4
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
0
Figure 26. Generating Special HBLK Patterns
Increasing H-Clock Width during HBLK
The AD9925 will also allow the H1 to H4 pulse width to be
increased during the HBLK interval. The H-clock pu
can increase by reducing the H-clock frequency (see Figure 27).
he HBLKWIDTH register, at Bank 1 Address 0x38, is a 3-bit
register that allows the H-clock frequency to be reduced by 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequen
only occur for H1 to H4 pulses that are located within t
BLK area.
H
Table 12. HBLK Width Register
Register
Length Range
HBLKWIDTH
3 b
1 to 1/14
lse width
T
cy will
he
Description
Controls H1 to H4 widt
during HBLK as a frac-
tion of pixel rate
0: same frequency as
pixel rate
1: 1/2 pixel frequency,
i.e., doubles the H1 to H4
pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
h
6: 1/12 pixel frequency
7: 1/14 pixel frequency
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 28 shows an exampl CCD layout. The horizontal register
ummy pixels, which will occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical black
(OB) lines at the front of the readout and 2 at the back of the
readout. The horizontal direction has 4 OB pixels in the front
back.
and 48 in the
Figure 29 shows the basic sequence layout to be used during the
effective pixel readout. The 48 OB pixels at the end of each
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval. The
HBLK, CLPOB, and PBLK parameters are programmed in the
vertical sequence registers.
line
g
contains 28 d
More elaborate clamping schemes may be used, such as addin
in a separate sequence to clamp during the entire shield OB
lines. This requires configuring a separate vertical sequence for
reading out the OB lines.
HBLK
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS
SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, OR 1/14 USING HBLKWIDTH REGISTER
H1/H3
H2/H4
1/F
PIX
2 × (1/F
PIX
)
0
Figure 27. Generating Wide H-Clock Pulses during HBLK Interval
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9925 | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9925BBCZ | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| AD9927 | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZRL | 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9925KBCZ | 制造商:Analog Devices 功能描述:12 BIT, 36 MSPS CCD SIGNAL PROCESSOR W/VERTICAL DRIVER - Bulk |
| AD9926BBCZ | 制造商:Analog Devices 功能描述: |
| AD9926BBCZRL | 制造商:Analog Devices 功能描述: |
| AD9927 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator |
| AD9927BBCZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 1.8V/3V 128-Pin CSP-BGA 制造商:Analog Devices 功能描述:IC 14BIT CCD SIGNAL PROCESSOR SMD |
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