參數(shù)資料
型號(hào)： AD9925BBCZRL
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 消費(fèi)家電
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝： 8 X 8 MM, 0.65 MM PITCH, LEAD FREE, PLASTIC, CSBGA-96
文件頁(yè)數(shù)： 65/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925BBCZRL
AD9925
Table 44. Register Map Selection
Address Data Bit Content
7F
[1:0]
Rev. A | Page 65 of 96
Default Value
0
Register Name
BANKSELECT
Register Description
Register Bank Access for Bank 1, Bank 2, and Bank 3.
0: Bank 1, 1: Bank 2, 2: Bank 3, and 3: Bank 1.
Table 45. AFE Operation Register Detail
ress
t Content
Add
Data Bi
00
[1:0]
[2]
[3]
fault Value
De
3
1
0
Name
PWRDOWN
CLPENABLE
CLPSPEED
Description
0: Normal Operation, 1: Standby 1, 2: Standby 2, 3: Standby 3.
0: Disable OB Clamp, 1: Enable OB Clamp.
0: Select Normal OB Clamp Settling, 1: Select Fast OB Clamp
Settling.
1: Select Temporary Fast Clamping When VGA Gain Is Up-
dated.
DOUT Value during PBLK: 0: Blank to 0, 1: Blank to Clamp
Level.
Test Operation Only. Set to 0.
0: Enable DC Restore Circuit, 1: Bypass DC Restore Circuit dur-
ing PBLK.
Test Use Only. Set to 0.
0: 0 dB, 1: 2 dB, 2: 4 dB, and 3: 0 dB.
[4]
0
FASTUPDATE
[5]
0
PBLK_LVL
[7:6]
[8]
0
0
TEST
DCBYP
[9]
[11:10]
0
0
TEST
CDSGAIN
Table
Add
03
46. A
ress
trol Registe
t Content
etail
fault Value
De
0
1
0
FE Con
Data Bi
[1:0]
[2]
[3]
r D
Name
TEST
TEST
DOUTDISABLE
Description
Test Use Only. Set to 0.
Test Use Only. Recommended setting is 0.
0 = Data Outputs Are Driven,
1 = Data Outputs Are Three-Stated.
0 = Latch Data Outputs with DOUT Phase,
1 = Output Latch Transparent.
0 = Binary Encode Data Outputs,
1 = Gray Encode Data Outputs.
[4]
0
DOUTLATCH
[5]
0
GRAYENCODE
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