RMIDSCV Red Channel Midscale Clamp Voltage Output" />
參數(shù)資料
型號(hào): AD9887AKSZ-140
廠商: Analog Devices Inc
文件頁(yè)數(shù): 7/52頁(yè)
文件大?。?/td> 0K
描述: IC INTRFACE ANALOG/DVI 160-MQFP
標(biāo)準(zhǔn)包裝: 24
應(yīng)用: 圖形卡,VGA 接口
接口: 模擬和數(shù)字
電源電壓: 3.15 V ~ 3.45 V
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-MQFP(28x28)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁(yè)面: 788 (CN2011-ZH PDF)
AD9887A
Rev. B | Page 15 of 52
RMIDSCV
Red Channel Midscale Clamp Voltage Output
GMIDSCV
Green Channel Midscale Clamp Voltage Output
BMIDSCV
Blue Channel Midscale Clamp Voltage Output
RCLAMPV
Red Channel Midscale Clamp Voltage Input
GCLAMPV
Green Channel Midscale Clamp Voltage Input
BCLAMPV
Blue Channel Midscale Clamp Voltage Input
These pins are part of the circuit that provides a
voltage reference for midscale clamping used in the
capture of YUV and YPbPr input signals. These
pins should be grounded through 0.1 μF capacitors,
as shown in Figure 4.
Data Clock Outputs
DATACK Data Output Clock
DATACK Data Output Clock Complement
These differential data clock output signals are used to
strobe the output data and HSOUT into external logic.
These signals are produced by the internal clock
generator and are synchronous with the internal
pixel sampling clock.
When the AD9887A is operated in single-channel
mode, the output frequency is equal to the pixel
sampling frequency. When the AD9887A is operated
in dual-channel mode, the clock frequency is half
the pixel frequency.
When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted as
well. The Data, DATACK, DATACK, and HSOUT
outputs are moved; therefore, the timing
relationship among the signals is maintained.
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