參數(shù)資料
型號： AD9887AKSZ-140
廠商： Analog Devices Inc
文件頁數(shù)： 26/52頁
文件大?。?/td> 0K
描述： IC INTRFACE ANALOG/DVI 160-MQFP
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 圖形卡，VGA 接口
接口： 模擬和數(shù)字
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-MQFP（28x28）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁面： 788 (CN2011-ZH PDF)
AD9887A
Rev. B | Page 32 of 52
2-WIRE SERIAL REGISTER MAP
The AD9887A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write
and read the control registers through the 2-line serial interface port.
Table 9. Control Register Map
Address
Read and
Write, or
Read Only
Bits
Default
Value
Register Name
Description
0x00
RO
7:0
Chip Revision
Bit 7 through Bit 4 represent functional revisions to the analog
interface. Bit 3 through Bit 0 represent nonfunctional related
revisions. Revision 0 = 0000 0000.
0x01
R/W
7:0
01101001
PLL Divide Ratio
MSBs
This register is for Bits[11:4] of the PLL divider. Larger values mean the
PLL operates at a faster rate. This register should be loaded first when
a change is needed. (This gives the PLL more time to lock.)1
0x02
R/W
7:4
1101****
PLL Divide Ratio
LSBs
This register is for Bits[3:0] of the PLL divider. Links to the PLL divide
ratio MSBs to make a 12-bit value.1
0x03
R/W
7:2
1*******
Clock Generator
Controls
Bit 7—Must be set to 1 for proper device operation.
*01*****
Bits[6:5]—VCO Range Select. Selects VCO frequency range (see the
PLL section).
***001**
Bits[4:2]—Charge-Pump Current. Varies the current that drives the
low-pass filter (see the PLL section).
0x04
R/W
7:3
10000***
Clock Phase Adjust
Clock Phase Adjust. Larger values mean more delay. (1 LSB = T/32)
0x05
R/W
7:0
10000000
Clamp Placement
Places the clamp signal an integer number of clock periods after the
trailing edge of the Hsync signal.
0x06
R/W
7:0
10000000
Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
0x07
R/W
7:0
00100000
Hsync Output
Pulse Width
Sets the number of pixel clocks that HSOUT remains active.
0x08
R/W
7:0
10000000
REDGAIN
Controls ADC input range (contrast) of red channel. Bigger values
result in less contrast.
0x09
R/W
7:0
10000000
GREENGAIN
Controls ADC input range (contrast) of green channel. Bigger values
result in less contrast.
0x0A
R/W
7:0
10000000
BLUEGAIN
Controls ADC input range (contrast) of blue channel. Bigger values
result in less contrast.
0x0B
R/W
7:1
1000000*
REDOFST
Controls dc offset (brightness) of red channel. Bigger values decrease
brightness.
0x0C
R/W
7:1
1000000*
GREENOFST
Controls dc offset (brightness) of green channel. Bigger values
decrease brightness.
0x0D
R/W
7:1
1000000*
BLUEOFST
Controls dc offset (brightness) of blue channel. Bigger values decrease
brightness.
0x0E
R/W
7:3
1*******
Mode Control 1
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. Logic 0 = single-channel mode; Logic 1 = dual-channel mode.
*1******
Bit 6—Output Mode. Determines interleaved or parallel output mode.
Logic 0 = interleaved mode; Logic 1 = parallel mode.
**0*****
Bit 5—Output Port Phase (OUTPHASE). Determines which port outputs
the first data byte after Hsync. Logic 0 = B port; Logic 1 = A port.
***0****
Bit 4—HSYNC Output Polarity. Logic 0 = logic high sync; Logic 1 =
logic low sync.
****0***
Bit 3—VSYNC Output Invert. Logic 0 = invert; Logic 1 = no invert.
0x0F
R/W
7:0
1*******
PLL and Clamp
Control
Bit 7—HSYNC Input Polarity. Indicates the polarity of incoming HSYNC
signal to the PLL. Logic 0 = active low; Logic 1 = active high.
*1******
Bit 6—COAST Input Polarity. Changes polarity of external coast signal.
Logic 0 = active low; Logic 1 = active high.
**0*****
Bit 5—Clamp Input Signal Source (EXTCLMP). Chooses between HSYNC
for CLAMP signal and another external signal to be used for clamping.
Logic 0 = HSYNC; Logic 1 = externally provided clamp signal.
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