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參數(shù)資料
| 型號(hào)： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/52頁 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 19 of 52
ADC
DAC
OFFSET
REF
x1.2
IN
CLAMP
VOFF
02838-010
7
GAIN
8
Figure 5. ADC Block Diagram (Single-Channel Output)
02838-005
GAIN
0xFF
0x00
INP
U
T
RANGE
(V
)
1.0
0.5
0
OFFSET = 0x00
OFFSET = 0x3F
OFFSET = 0x7F
OFFSET = 0x00
OFFSET = 0x7F
OFFSET = 0x3F
Figure 6. Gain and Offset Control
1V
INP
U
T
RANGE
VOFF
(128 CODES)
INP
U
T
RANGE
0.5V
VOFF
(128 CODES)
OFFSET
RANGE
0V
OFFS
E
T
RANGE
02838-011
Figure 7. Relationship of Offset Range to Input Range
SYNC-ON-GREEN INPUT
The sync-on-green input operates in two steps. First, with the
aid of a negative peak detector, it sets a baseline clamp level
from the incoming video signal. Second, it sets the sync trigger
level (nominally 150 mV above the negative peak). The exact
trigger level is variable and can be programmed via Register 0x11.
The sync-on-green input must be ac-coupled to the green analog
input through its own capacitor, as shown in Figure 8.
The value of the capacitor must be 1 nF ± 20%. If sync-on-green
is not used, this connection is not required and SOGIN should
be left unconnected. (Note that the sync-on-green signal is always
negative polarity.) See the Theory of Operation—Sync Processing
section for more information.
02838-006
GAIN
SOGIN
1nF
RAIN
47nF
BAIN
47nF
Figure 8. Typical Clamp Configuration for RGB and YUV Applications
CLOCK GENERATION
A phase-locked loop (PLL) is used to generate the pixel clock.
The HSYNC input provides a reference frequency for the PLL.
A voltage-controlled oscillator (VCO) generates a much higher
pixel clock frequency. This is divided by the PLL divide value
(MSBs in Register 0x01 and LSBs in Register 0x02) and phase
compared with the HSYNC input. Any error is used to shift the
VCO frequency and maintain lock between the two signals.
The stability of this clock is important for providing the clearest,
most stable image. During each pixel time, there is a period when
the signal slews from the old pixel amplitude and settles at its
new value. Then, the input voltage is stable until the signal slews
to a new value (see Figure 9). The ratio of the slewing time to the
stable time is a function of the bandwidth of the graphics DAC,
the bandwidth of the transmission system (cable and termination),
and the overall pixel rate. Clearly, if the dynamic characteristics
of the system remain fixed, the slewing and settling times are
likewise fixed. Subtract these times from the total pixel period to
determine the stable period. At higher pixel frequencies, both the
total cycle time and stable pixel time are shorter.
02838-007
PIXEL CLOCK
INVALID SAMPLE TIMES
Figure 9. Pixel Sampling Times
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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