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參數(shù)資料
| 型號： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 29 of 52
THEORY OF OPERATION—DIGITAL INTERFACE
CAPTURING ENCODED DATA
The first step in recovering encoded data is to capture the raw data.
To accomplish this, the AD9887A uses a high speed, phase-locked
loop (PLL) to generate clocks capable of oversampling the data
at the correct frequencies. The data capture circuitry continuously
monitors the incoming data during horizontal and vertical
blanking periods (when DE is low) and independently selects
the best sampling phase for each data channel. The phase infor-
mation is stored and used until the next blanking period (one
video line).
DATA FRAMES
The digital interface data is captured in groups, called data
frames, of 10 bits each. During the active data period, each
frame is made up of nine encoded video data bits and one dc-
balancing bit. The data capture block receives this data serially,
but outputs each frame in parallel, 10-bit words.
SPECIAL CHARACTERS
During periods of horizontal or vertical blanking (when DE is
low), the digital transmitter transmits special characters that are
used to set the video frame boundaries and the phase recovery
loop for each channel. There are four special characters that can
be received. They are used to identify the top, bottom, left side,
and right side of each video frame. The data receiver can differ-
entiate these special characters from active data, because the
special characters have a different number of transitions per
data frame.
CHANNEL RESYNCHRONIZATION
The purpose of the channel resynchronization block is to
resynchronize the three data channels to a single internal data
clock. Even if all three data channels are on different phases of
the PLL clock (0°, 120°, and 240°), this block can resynchronize
the channels from a worst-case skew of one full input period
(8.93 ns at 170 MHz).
DATA DECODER
The data decoder receives frames of data and sync signals from
the data capture block in 10-bit, parallel words and decodes
them into groups of eight RGB/YUV bits, two control bits, and
a data enable (DE) bit.
HDCP
The AD9887A contains circuitry necessary for decrypting
a high-bandwidth digital content protection (HDCP) encoded
DVI video stream. A typical HDCP implementation is shown in
Figure 32. Several features of the AD9887A make decryption
possible and ease the implementation of HDCP.
The basic components of HDCP are included in the AD9887A.
A slave serial bus connects to the DDC clock and the DDC data
pins on the DVI connector to allow the HDCP-enabled DVI
transmitter to coordinate the HDCP algorithm with the
AD9887A. A second serial port (MDA/MCL) allows the
AD9887A to read the HDCP keys and key selection vector
(KSV) stored in an external serial EEPROM. When transmitting
encrypted video, the DVI transmitter enables HDCP through
the DDC port.
The AD9887A then decodes the DVI stream using information
provided by the transmitter, HDCP keys, and KSV. The AD9887A
allows the MDA and MCL pins to be three-state, using the
MDA/MCL three-state bit (Register 0x1B, Bit 7) in the
configuration registers. The three-state feature allows the EEPROM
to be programmed in-circuit. The MDA/MCL port must be
three-state before attempting to program the EEPROM using an
external master. The keys are stored in an I2C-compatible 3.3 V
serial EEPROM of at least 512 bytes. The EEPROM should have
a device address of 0xA0.
Proprietary software licensed from Analog Devices, Inc. encrypts
the keys and creates properly formatted EEPROM images for
use in a production environment. Encrypting the keys helps
maintain the confidentiality of the HDCP keys, as required by
the HDCP v1.0 specification. The AD9887A includes hardware
for decrypting the keys in the external EEPROM.
ADI provides a royalty-free license for the proprietary software
needed by customers to encrypt the keys between the AD9887A
and the EEPROM only after customers provide evidence of a
completed HDCP Adopter’s License Agreement and sign the Analog
Devices Software License Agreement. The Adopter’s License
Agreement is maintained by Digital Content Protection, LLC
and can be downloaded from www.digital-cp.com. To obtain the
Analog Devices Software License Agreement, contact the Display
Electronics Product Line directly by sending an email to
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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