- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9887AKSZ-140 (Analog Devices Inc)IC INTRFACE ANALOG/DVI 160-MQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD9887A
Rev. B | Page 20 of 52
02838-008
PIXEL CLOCK (MHz)
25.1
31.5
36.0
40.0
50.0
58.2
65.0
75.0
78.7
85.5
94.5
108.0
135.0
158.0
162.0
176.0
JITTER
(%)
6
5
4
3
2
1
0
The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO range register sets this operating range.
Because there are only three possible regions, just 2 LSBs of
the VCO range register are used. The frequency ranges for
the lowest and highest regions are shown in Table 5.
Table 5. VCO Frequency Ranges
PV1
PV0
Pixel Clock Range (MHz)
0
12 to 37
0
1
37 to 74
1
0
74 to 140
1
140 to 170
Figure 10. Pixel Clock Jitter vs. Frequency
The 3-Bit Charge-Pump Current Register. This register
allows the current that drives the low-pass loop filter to be
varied. The possible current values are listed in Table 6.
Any jitter in the clock reduces the precision with which the
sampling time can be determined and, thus, must be subtracted
from the stable pixel time. The AD9887A clock generation
circuit is designed to minimize jitter to less than 6% of the total
pixel time in all operating modes, making its effect on valid
sampling time negligible (see Figure 10).
Table 6. Charge-Pump Current/Control Bits
Ip2
Ip1
Ip0
Current (μA)
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
The PLL characteristics are determined by the loop-filter design,
the PLL charge-pump current, and the VCO range setting. The
loop-filter design is illustrated in Figure 11. Recommended settings
of VCO range and charge-pump current for VESA standard
display modes are listed in Table 7.
CP
0.0039
μF
CZ
0.039
μF
RZ
3.3k
Ω
FILT
PVD
02838-009
The 5-Bit Phase Adjust Register. The phase of the
generated sampling clock can be shifted to locate an
optimum sampling point within a clock cycle. The phase-
adjust register provides 32 phase-shift steps of 11.25° each.
The Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjustment is operational
even if the pixel clock is provided externally. The COAST
signal allows the PLL to continue to run at the same frequency
in the absence of the incoming Hsync signal. This can be
used during the vertical sync period or any other time that
the Hsync signal is unavailable. The polarity of the coast
signal can be set through the COAST polarity bit, and the
polarity of the Hsync signal can be set through the HSYNC
polarity bit. If not using automatic polarity detection, set
the HSYNC and COAST polarity bits to match the polarity
of their respective signals.
Figure 11. PLL Loop-Filter Detail
The following programmable registers are provided to optimize
the performance of the PLL:
The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 12 MHz to 170 MHz. The
divisor register controls the exact multiplication factor. This
register can be set to any value between 221 and 4095. (The
divide ratio used is the programmed divide ratio plus one.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9888KSZ-170 | IC ANALOG INTRFC 170MSPS 128MQFP |
| AD9895KBCZRL | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| AD9910BSVZ-REEL | IC DDS 1GSPS 14BIT PAR 100TQFP |
| AD9911BCPZ-REEL7 | IC DDS 500MSPS DAC 10BIT 56LFCSP |
| AD9912ABCPZ | IC DDS 1GSPS DAC 14BIT 64LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。