參數(shù)資料
型號(hào)： AD9887AKSZ-140
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/52頁(yè)
文件大?。?/td> 0K
描述： IC INTRFACE ANALOG/DVI 160-MQFP
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 圖形卡，VGA 接口
接口： 模擬和數(shù)字
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-MQFP（28x28）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
AD9887A
Rev. B | Page 23 of 52
TIMING—ANALOG INTERFACE
Three things happen to Hsync in the AD9887A. First, the polarity
of the HSYNC input is determined and, thus, has a known output
polarity. The known output polarity can be programmed either
active high or active low (Register 0x04, Bit 4). Second, HSOUT
is aligned with DATACK and data outputs. Third, the duration
of HSOUT (in pixel clocks) is set via Register 0x07. Use the
HSOUT signal to drive the rest of the display system.
The timing diagrams (Figure 18 through Figure 27) show the
operation of the AD9887A analog interface in all clock modes.
The part establishes timing by sending the pixel corresponding
with the leading edge of Hsync to Data Port A. In dual-channel
mode, the next sample is sent to Data Port B. Subsequent samples
are alternated between the A and B data ports. In single-channel
mode, data is only sent to Data Port A, and Data Port B is placed
in a high impedance state.
Coast Timing
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the coast
input and function are unnecessary and should not be used.
In some systems, however, Hsync is disturbed during the vertical
sync (Vsync) period, and sometimes Hsync pulses disappear.
In other systems, such as those that use composite sync (Csync)
signals or those that embed sync-on-green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it attempts to lock on to this new frequency and changes
frequency by the end of the Vsync period. It then requires a few
lines of correct Hsync timing to recover at the beginning of a new
frame, resulting in a tearing of the image at the top of the display.
The output data clock signal is created so that its rising edge
always occurs between transitions of Data Port A and can be
used to latch the output data externally.
PXCK
ANY OUTPUT
SIGNAL
DATACK
(OUTPUT)
tSKEW
tDCYCLE
tPER
DATA OUT
0
28
38
-0
19
Figure 17. Analog Output Timing
Hsync Timing
Horizontal sync is processed in the AD9887A to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
The coast input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and holds the
clock at its current frequency. The PLL can operate in this manner
for several lines without significant frequency drift.
The HSYNC input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted with respect
to Hsync through a full 360° in 32 steps via the phase adjust
register to optimize the pixel sampling time. Display systems
use Hsync to align memory and display write cycles; therefore,
it is important to have a stable timing relationship between the
HSYNC output (HSOUT) and data clock (DATACK).
Coast can be provided by the graphics controller, or it can be
internally generated by the AD9887A sync processing engine.
P0
P1
P2
P3
P4
P5
P6
P7
D1
D2
D3
D4
D5
D6
RGBIN
HSYNC
PXCK
HS
ADCCK
DATACK
DOUTA
HSOUT
02
83
8-
0
20
7-PIPE DELAY
Figure 18. Single-Channel Mode (Analog Interface)
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AD9887AKSZ-1401 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display
AD9887AKSZ-170 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
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