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參數(shù)資料
| 型號： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/52頁 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 37 of 52
0x0C 7:1
Green Channel Offset Adjust (GREENOFST)
A 7-bit offset binary word that sets the dc offset of the
green channel. See REDOFST (0B).
0x0D 7:1
Blue Channel Offset Adjust (BLUEOFST)
A 7-bit offset binary word that sets the dc offset of the
blue channel. See REDOFST (0B).
Mode Control 1
0x0E 7
Channel Mode
A bit that determines whether all pixels are presented to
a single port (Port A), or if alternating pixels are demulti-
plexed to Port A and Port B.
Table 12. Channel Mode Settings
DEMUX
Function
0
All data goes to Port A
1
Alternate pixels go to Port A and Port B
When DEMUX = 0, Port B outputs are in a high imped-
ance state. The maximum data rate for single-port mode
is 100 MHz. The timing diagrams show the effects of
this option.
The power-up default value is 1.
0x0E 6
Output Mode
A bit that determines whether all pixels are
simultaneously presented to Port A and Port B upon
every second DATACK rising edge or alternately
presented to Port A and Port B upon successive
DATACK rising edges.
Table 13. Output Mode Settings
PARALLEL
Function
0
Data is interleaved
1
Data is simultaneous upon every other data clock
When in single-port mode (DEMUX = 0), this bit is
ignored. The timing diagrams (Figure 18 through Figure 27
and Figure 37 through Figure 39) show the effects of this
option.
The power-up default value is PARALLEL = 1.
0x0E 5
Output Port Phase
One bit that determines whether even or odd pixels go to
Port A.
Table 14. Output Port Phase (OUTPHASE) Settings
OUTPHASE
First Pixel After Hsync
1
Port B
0
Port A
In normal operation (OUTPHASE = 0) when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented to Port A,
every subsequent odd sample goes to Port A, and all
even samples go to Port B.
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
When DEMUX = 0, this bit is ignored because data
always comes out of only Port A.
0x0E 4
HSYNC Output Polarity
One bit that determines the polarity of the HSYNC
output and the SOG output. Table 15 shows the effect of
this option. SYNC indicates the logic state of the sync
pulse.
Table 15. HSYNC Output Polarity Settings
Setting
HSYNC
0
Logic 1 (negative polarity)
1
Logic 0 (positive polarity)
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
0x0E 3
VSYNC Output Invert
One bit that inverts the polarity of the VSYNC output.
Table 16 shows the effect of this option.
Table 16. VSYNC Output Polarity Settings
Setting
VSYNC Output
0
Invert
1
No invert
The default setting for this register is 1. This option
works on both the analog and digital interfaces.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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