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參數(shù)資料
| 型號： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 43 of 52
0x17 7:0
Precoast
This register allows the coast signal to be applied prior to
the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. This register defines the
number of edges that are filtered before Vsync on a
composite sync.
The default is 0.
0x18 7:0
Postcoast
This register allows the coast signal to be applied
following the Vsync signal. This is necessary when
postequalization pulses are present. This register defines
the number of edges that are filtered after Vsync on a
composite sync.
The default is 0.
0x19 7:0
Test
Must be set to default.
0x1A 7:0
Test
Must be set to 0x41 for proper operation.
0x1B 7:0
Test
Must be set to 0x00 for autogain mode and 0x10 for
manual-gain mode.
0x1C 7:3
Test
Must be set to 00000*** for autogain mode and 00101***
for manual-gain mode.
0x1C 2
CbCr Output Order
In 4:2:2 mode, the red and blue channels can be
interchanged to help satisfy board layout or timing
requirements, but the green channel must be configured
for Y. Register 0x1C, Bit 2, controls the order that the
U/V (CbCr) data is output. If this bit is high, the red
channel data precedes the blue channel data. If this bit is
low, the blue channel data precedes the red channel data.
See the example in Table 51.
Table 51. 4:2:2 Input/Output Configuration
Channel
Input
Connection
Output Format
Red
Y
V/U if 0x1C Bit 2 = 1;
U/V if 0x1C Bit 2 = 0
Green
Y
Blue
U
High impedance
0x1C 1
Test Bits
Must be set to 0 for standard input sampling.
0x1C 0
4:2:2 Output Mode Select
4:2:2 mode can be used to reduce the number of data
lines used from 24 to 16 for applications using YUV,
YCbCr, or YPbPr graphics signals. See Figure 27 for a
timing diagram for this mode.
Table 52. 4:2:2 Output Mode Select
Select
Output Mode
1
4:4:4
0
4:2:2
0x1D 6
HDCP Keys Detected
This bit indicates the presence of HDCP keys read from
the external EEPROM.
Table 53. HDCP Key Status
Select
HDCP Key Status
1
HDCP keys present
0
HDCP keys not present
0x1E 7:0
Test Register
Must be set to 0xFF for proper operation.
0x1F 7:0
Test Register
Must be set to 0x84 for proper operation.
0x20 7
HDCP A0 Serial Address Bit
This bit sets the value of the A0 bit for the DDC
serial port.
Table 54. HDCP A0 Serial Address
Select
Serial Address
1
A0 bit = 1, address = 0x76
0
A0 bit = 0, address = 0x74
The default setting is 0.
0x20 6
MDA Pin Select
This bit sets the function of Pin 49 to MDA when set at 1.
Table 55. MDA Pin Select
Select
Output Mode
1
Pin 49 = MDA for HDCP
0
Pin 49 = CTL3 signal
The default setting is 0.
0x20 5
Analog Input Bandwidth Control
This bit controls the analog input bandwidth.
Table 56. Analog Input Bandwidth Control
Select
Input Bandwidth
0
High analog input bandwidth
1
Low analog input bandwidth
The default setting 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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