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參數(shù)資料
| 型號： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標準包裝： | 24 |
| 應用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應商設備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 13 of 52
PIN FUNCTION DETAILS—ANALOG INTERFACE
Analog Video Data Inputs
RAIN
Analog Input for Red Channel
GAIN
Analog Input for Green Channel
BAIN
Analog Input for Blue Channel
These are the high impedance inputs that accept
graphics signals from the red, green, and blue
channels, respectively. For RGB, the three channels
are identical and can be used for any color, but colors
are assigned for convenient reference. For proper
4:2:2 formatting in a YUV application, the Y channel
must be connected to the GAIN input, U must be
connected to the BAIN input, and V must be
connected to the RAIN input.
These pins accommodate input signals ranging from
0.5 V to 1.0 V full scale. Signals should be ac-coupled
to these pins to support clamp operation.
External Inputs
HSYNC
Horizontal Sync Input
This input receives a logic signal that establishes the
horizontal timing reference and provides the fre-
quency reference for pixel clock generation.
The logic sense of this pin is controlled by Serial
Register 0x0F, Bit 7 (Hsync polarity). Only the leading
edge of Hsync is active; the trailing edge is ignored.
When Hsync polarity = 0, the falling edge of Hsync
is used. When Hsync polarity = 1, the rising edge is
active.
The input includes a Schmitt trigger for noise
immunity with a nominal input threshold of 1.5 V.
Electrostatic discharge (ESD) protection diodes
conduct heavily if this pin is driven more than 0.5 V
above the maximum tolerance voltage (3.3 V) or
more than 0.5 V below ground.
VSYNC
Vertical Sync Input
This is the input for vertical sync.
Sync/Clock Inputs
SOGIN
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the green
channel. The pin is connected to a high speed com-
parator with an internally generated threshold that is
0.15 V above the negative peak of the input signal.
When connected to an ac-coupled graphics signal
with embedded sync, it produces a noninverting
digital output on SOGOUT.
When not used, leave this input unconnected. For
more details on this function and how it should be
configured, refer to the Sync-on-Green Input section.
CLAMP
External Clamp Input (Optional)
This logic input can be used to define the time
during which the input signal is clamped to the
reference dc level (ground for RGB, midscale for
YUV). It should be used when the reference dc level
is known to be present on the analog input channels,
typically during a period called the back porch of
the graphics signal following Hsync. The CLAMP
pin is enabled by setting control bit EXTCLMP to 1
(the default at power-up is 0). When disabled, this
pin is ignored and the clamp timing is determined
internally by counting the delay and duration from
the trailing edge of the HSYNC input. The logic
sense of this pin is controlled by CLAMPOL. When
not used, this pin must be grounded and EXTCLMP
must be programmed to 0.
COAST
Clock Generator Coast Input (Optional)
This input can be used to stop the pixel clock generator
from synchronizing with Hsync while maintaining
the clock at its current frequency and phase. This is
useful when processing signals from sources that
fail to produce horizontal sync pulses when in the
vertical interval. The coast signal is generally not
required for PC-generated signals. For applications
requiring coast, it is provided through the internal
coast found in the sync processing engine.
The logic sense of this pin is controlled by coast
polarity. When not used, this pin can be grounded
with coast polarity programmed to 1, or tied high
with coast polarity programmed to 0. Coast polarity
defaults to 1 at power-up.
CKEXT
External Clock Input (Optional)
This pin can be used to provide an external clock to
the AD9887A in place of the clock internally
generated from HSYNC. It is enabled by program-
ming CKEXT to 1. When an external clock is used,
all other internal functions, including the clock
phase adjustment, operate normally. When not
used, this pin should be tied to VDD or to ground
and CKEXT should be programmed to 0.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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