參數(shù)資料
型號(hào)： AD9887AKSZ-140
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/52頁(yè)
文件大?。?/td> 0K
描述： IC INTRFACE ANALOG/DVI 160-MQFP
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 圖形卡，VGA 接口
接口： 模擬和數(shù)字
電源電壓： 3.15 V ~ 3.45 V
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-MQFP（28x28）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
AD9887A
Rev. B | Page 34 of 52
Address
Read and
Write, or
Read Only
Bits
Default
Value
Register Name
Description
*****0**
Bit 2—Output Vsync Select. Logic 0 selects raw Vsync as the output
Vsync. Logic 1 selects sync separator output as the active Vsync. Note
that the indicated Vsync is used only if Bit 3 is set to Logic 1.
******0*
Bit 1—COAST Select. Logic 0 selects the COAST input pin used for the
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
*******1
Bit 0—PWRDN. Full Chip Power-Down, active low. Logic 0 = full chip
power-down; Logic 1 = normal.
0x13
R/W
7:0
00100000
Sync Separator
Threshold
Sync Separator Threshold. Sets the number of clock cycles that the sync
separator counts before toggling high or low. This should be set to a
number greater than the maximum Hsync or equalization pulse width.
0x14
R/W
7:0
***1****
Control Bits
Bit 4—Must be set to 1 for proper operation.
****0***
Bit 3—Must be set to 0 for proper operation.
*****0**
Bit 2—Scan Enable. Logic 0 = scan function disabled; Logic 1 = scan
function enabled.
******0*
Bit 1—COAST Input Polarity Override. Logic 0 = polarity determined by
chip; Logic 1 = polarity determined by user via Bit 6 in Register 0x0F.
*******0
Bit 0—HSYNC Input Polarity Override. Logic 0 = polarity determined
by chip; Logic 1 = polarity determined by user via Bit 7 in Register 0x0F.
0x15
RO
7:5
0*******
Polarity Status
Bit 7—Hsync Input Polarity Status. Logic 0 = active low; Logic 1 =
active high.
*0******
Bit 6—Vsync Output Polarity Status. Logic 0 = active high; Logic 1 =
active low.
**0*****
Bit 5—Coast Input Polarity Status. Logic 0 = active low; Logic 1 =
active high.
0x16
R/W
7:2
10111***
Control Bits
Bits[7:3]—Sync-on-Green Slicer Threshold.
*****1**
Bit 2—Must be set to 0 for proper operation.
0x17
R/W
7:0
00000000
Precoast
Sets the number of Hsyncs prior to Vsync before which coast goes
active.
0x18
R/W
7:0
00000000
Postcoast
Sets the number of Hsyncs following Vsync before coast goes active.
0x19
R/W
7:0
00000000
Test Register
Must be set to default for proper operation.
0x1A
R/W
7:0
11111111
Test
Must be set to 01000001 for proper operation.
0x1B
R/W
7:0
00000000
Set to 0x00 for autogain mode and 0x10 for manual-gain mode
0x1C
R/W
7:0
00000***
Bits [7:3]—Set to 00000*** for autogain mode and 00101*** for
manual-gain mode
*****1**
Bit 2—CbCr Output Order.
******1*
Bit 1—Must be set to 0 for standard input sampling.
*******1
4:2:2 Control
Bit 0—Output Format Mode Select. Logic 1 = 4:4:4 mode; Logic 0 =
4:2:2 mode.
0x1D
RO
7:0
*_*****
HDCP Keys Detected. Logic 0 = not detected; Logic 1 = detected.
0x1E
R/W
7:0
11111111
Must set to 0xFF for proper operation.
0x1F
R/W
7:0
10000100
Must set to 0x84 for proper operation.
0x20
R/W
7:0
0*******
Bit 7—HDCP A0 Serial Address Bit. For Logic 0, Address = 0x74. For
Logic 1, Address = 0x76.
*0******
Bit 6—MDA Pin Select. For Logic 0, Pin 49 = Ctrl3 signal. For Logic 1,
Pin 49 = MDA for HDCP.
**0*****
Bit 5—Analog Input Bandwidth Control. Logic 0 = high.
***0****
Bit 4—MDA/MCL Three-State. Logic 0 = three-state; Logic 1 = normal
operation.
****1***
Bit 3—External Oscillator. Logic 1 = internal; Logic 0 = use external
oscillator on A0.
*****0**
Normal Operation.
0x21
R/W
7:0
00000000
TDMS Gain Control
Set to 0x00 for autogain mode and 0x64 for manual-gain mode.
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