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參數(shù)資料
| 型號： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/52頁 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標準包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 48 of 52
THEORY OF OPERATION—SYNC PROCESSING
SYNC STRIPPER
The purpose of the sync stripper is to extract the sync signal
from the green graphics channel. A sync signal is not present on
all graphics systems, only those with sync-on-green. The sync
signal is extracted from the green channel in a two-step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator
with a trigger level that is 0.15 V above the clamped level. The
output signal is typically a composite sync signal containing
both Hsync and Vsync.
SYNC SEPARATOR
A sync separator extracts the Vsync signal from a composite
sync signal by using a low-pass filter-like or integrator-like
operation. It works on the idea that the Vsync signal stays active
much longer than the Hsync signal. Therefore, it rejects any signal
shorter than a threshold value, which is somewhere in the range
between an Hsync pulse width and a Vsync pulse width.
The sync separator on the AD9887A is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.)
The basic idea is that the counter counts up when Hsync pulses
are present. Since Hsync pulses are relatively short in width, the
counter only reaches a value of N before the pulse ends. It then
starts counting down, eventually reaching 0 before the next
Hsync pulse arrives. The specific value of N varies among video
modes, but is always less than 255. For example, with a 1 μs
width Hsync, the counter only reaches 5 (1 μs/200 ns = 5).
When Vsync is present on the composite sync, the counter also
counts up. Because the Vsync signal is much longer, it counts to
a higher number M. For most video modes, M is at least 255.
Therefore, Vsync can be detected on the composite sync signal
by detecting when the counter counts to higher than N. The
specific count that triggers detection, the threshold count (T),
can be programmed through the serial Register 0x0F. Once
Vsync is detected, there is a similar process to detect when it
becomes inactive. Upon detection, the counter first resets to 0,
then counts up when Vsync disappears. Similar to the previous
case, it detects the absence of Vsync when the counter reaches
T. In this way, it rejects noise and/or serration pulses. Once
Vsync is detected to be absent, the counter resets to 0 and
begins the cycle again.
SYNC STRIPPER
NEGATIVE PEAK
CLAMP
COMP
SYNC
SOG
HSYNC IN
HSYNC OUT
PIXEL CLOCK
MUX 1
SYNC SEPARATOR
INTEGRATOR
VSYNC
SOG OUT
HSYNC OUT
VSYNC OUT
MUX 4
VSYNC IN
1/S
PLL
HSYNC
ACTIVITY
DETECT
AD9887A
CLOCK
GENERATOR
COAST
02838-041
ACTIVITY
DETECT
ACTIVITY
DETECT
POLARITY
DETECT
POLARITY
DETECT
POLARITY
DETECT
MUX 2
MUX 3
POLARITY
INVERT
Figure 43. Sync Processing Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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