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| 型號(hào)： | AD9887AKSZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 應(yīng)用： | 圖形卡，VGA 接口 |
| 接口： | 模擬和數(shù)字 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-MQFP（28x28） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 49 of 52
PCB LAYOUT RECOMMENDATIONS
The AD9887A is a high performance, high speed analog device.
To optimize its performance, it is important to have a well laid
out board. The following is a guide for designing a board using
the AD9887A.
ANALOG INTERFACE INPUTS
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs.
This is accomplished by placing the AD9887A as close as
possible to the graphics VGA connector. Long input trace
lengths are undesirable because they pick up noise from
the board and other external sources.
Place the 75 Ω termination resistors as close to the AD9887A
chip as possible. Any additional trace length between the
termination resistors and the input of the AD9887A
increases the magnitude of reflections, which corrupts the
graphics signal.
Use 75 Ω matched impedance traces. Trace impedances
other than 75 Ω also increase the chance of reflections.
The AD9887A has very high input bandwidth (330 MHz).
Although this is desirable for acquiring a high resolution PC
graphics signal with fast edges, it means that it also captures any
high frequency noise present. Therefore, it is important to reduce
the amount of noise coupled to the inputs. Avoid running any
digital traces near the analog inputs. Due to the high bandwidth
of the AD9887A, sometimes low-pass filtering the analog inputs
can help reduce noise. (For many applications, filtering is unnec-
essary.) Experiments have shown that placing a series ferrite
bead in front of the 75 Ω termination resistor can filter out
excess noise. Specifically, the part used was the #2508051217Z0
from Fair-Rite, but each application might work best with a
different bead value. Alternatively, placing a 100 Ω to 120 Ω
resistor between the 75 Ω termination resistor and the input
coupling capacitor can also be beneficial.
DIGITAL INTERFACE INPUTS
Each differential input pair (Rx0+, Rx0, RxC+, RxC, and so
on) should be routed together using 50 Ω strip line routing
techniques kept as short as possible. No other components
should be placed on these inputs (for example, no clamping
diodes). Every effort should be made to route these signals on a
single layer (component layer) with no vias.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is when two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is only necessary to have one bypass
capacitor.
The fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
the side of the PC board opposite from the AD9887A, because
this interposes resistive vias in the path.
The bypass capacitors should physically be located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful regulation,
filtering, and bypassing. It is highly desirable to provide separate
regulated supplies for each of the analog circuitry groups (VD
and PVD).
Some graphics controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVD, from a different,
cleaner power source (for example, from a 12 V supply).
It is recommended to use a single ground plane for the entire
board. Experience shows that noise performance is the same or
better with a single ground plane. Using multiple ground planes
can be detrimental because each separate ground plane is
smaller and can result in long ground loops.
In some cases, using separate ground planes is unavoidable. For
these cases, it is recommended to place at least a single ground
plane under the AD9887A. The location of the split should be at
the receiver of the digital outputs. For these cases, it is even
more important to place components wisely because the current
loops are much longer, and current takes the path of least
resistance. An example of a current loop follows.
A
N
A
LO
G
GR
OU
ND
PLA
NE
POWER PLANE
AD9887A
DIG
ITA
L
O
U
T
P
U
T
TR
AC
E
DIG
ITAL
GROU
ND PLANE
D
IGITAL DATA R
ECEIV
ER
02838-042
Figure 44. Example of a Current Loop
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9887AKSZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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