
Philips Semiconductors
SPDIF Out
PRODUCT SPECIFICATION
10-5
10.14 MMIO REGISTER DESCRIPTION
Figure 10-4. SPDO unit status/control field MMIO layout.
MMIO_base
offset:
SPDO_STATUS (r/
0x10 4C00
SPDO_CTL (r/w)
0x10 4C04
SPDO_FREQ (r/w)
0x10 4C08
SPDO_BASE1 (r/w)
0x10 4C0C
FREQUENCY
BUF1_ACTIVE
SPDO_BASE2 (r/w)
0x10 4C10
BASE2
SPDO_SIZE (r/w)
0x10 4C14
SIZE (in bytes)
31
0
3
7
11
15
19
23
27
BASE1
UNDERRUN
HBE (Highway bandwidth error)
BUF2_EMPTY
RESET
TRANS_ENABLE
TRANS_MODE
LITTLE_ENDIAN
0
UDR_INTEN
HBE_INTEN
BUF2_INTEN
BUF1_INTEN
ACK_UDR
ACK_HBE
ACK_BUF2
ACK_BUF1
0
SLEEPLESS
BUF1_EMPTY
0
31
0
3
7
11
15
19
23
27
31
0
3
7
11
15
19
23
27
SPDO_TSTAMP (r/o)
0x10 4C18
TIMESTAMP
Table 10-4. SPDO_STATUS MMIO register
eld
type
description
BUF1_EMPTY
r/o
Sticky ag - set if DMA buffer 1 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF1.
BUF2_EMPTY
r/o
Sticky ag - set if DMA buffer 2 emp-
tied by the SPDO hardware. Can only
be cleared by software write to
ACK_BUF2.
HBE
r/o
Highway Bandwidth Error. Sticky ag -
set if internal SPDO buffers emptied
before new data brought from memory.
Refer to Section 10.17, “HBE and
Highway Latency.” Can be cleared
only by a software write to ACK_HBE.
UNDERRUN
r/o
Sticky ag - set if both DMA buffers
were emptied before a new full buffer
was assigned by the DSPCPU. The
hardware has performed a normal
buffer switch over and is emitting old
data. Can only be cleared by software
write to ACK_UDR.
BUF1_ACTIVE
r/o
Flag - set if the hardware is currently
emitting DMA buffer 1 data; negated
when emitting DMA buffer 2 data.
Table 10-5. SPDO_CTL MMIO register
eld
type
description
ACK_BUF1
w/o
Always reads as ‘0’. Write a ‘1’ here
to clear BUF1_EMPTY. This
informs SPDO that DMA buffer 1 is
now full. Writing a ‘0’ has no effect.
ACK_BUF2
w/o
Always reads as ‘0’. Write a ‘1’ here
to clear BUF2_EMPTY. This
informs SPDO that DMA buffer 2 is
now full. Writing a ‘0’ has no effect.
ACH_HBE
w/o
Always reads as ‘0’. Writing a ‘1’
here clears HBE.
ACK_UDR
w/o
Always reads as ‘0’. Writing a ‘1’
here clears UNDERRUN.
BUF1_INTEN
r/w
If BUF1_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
BUF2_INTEN
r/w
If BUF2_EMPTY asserted and this
bit asserted, the SRC 25 interrupt
line is asserted.
HBE_INTEN
r/w
If HBE asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.
UDR_INTEN
r/w
If UNDERRUN asserted and this bit
asserted, the SRC 25 interrupt line
is asserted.