
TM1300 Data Book
Philips Semiconductors
A-42
PRODUCT SPECIFICATION
IEEE status ags from oating-point divide
SYNTAX
[ IF r
guard ] fdivflags rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then
r
dest
← ieee_ags((oat)rsrc1 / (oat)rsrc2)
ATTRIBUTES
Function unit
ftough
Operation code
109
Number of operands
2
Modier
No
Modier range
—
Latency
17
Recovery
16
Issue slots
2
DESCRIPTION
The fdivflags operation computes the IEEE exceptions that would result from computing the quotient
r
src1
÷rsrc2 and stores a bit vector representing the exception ags into rdest. The argument values are in IEEE
single-precision oating-point format; the result is an integer bit vector. The bit vector stored in r
dest has the same
format as the IEEE exception bits in the PCSW. The exception ags in PCSW are left unchanged by this operation.
Rounding is according to the IEEE rounding mode bits in PCSW. If an argument is denormalized, zero is substituted
before computing the quotient, and the IFZ bit in the result is set. If the quotient would be denormalized, the OFZ bit in
the result is set.
The fdivflags operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB controls the
modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x7f7fffff (3.402823466e+38),
r40 = 0x3f800000 (1.0)
fdivflags r30 r40
→ r100
r100
← 0
r10 = 0,
r50 = 0x7f7fffff (3.402823466e+38)
r60 = 0x3e000000 (0.125)
IF r10 fdivflags r50 r60
→ r110 no change, since guard is false
r20 = 1,
r50 = 0x7f7fffff (3.402823466e+38)
r60 = 0x3e000000 (0.125)
IF r20 fdivflags r50 r60
→ r111 r111 ← 0xa (OVF INX)
r70 = 0x40400000 (3.0),
r80 = 0x00400000 (5.877471754e–39)
fdivflags r70 r80
→ r112
r112
← 0x21 (IFZ DBZ)
r85 = 0x7f800000 (+INF),
r86 = 0xff800000 (–INF)
fdivflags r85 r86
→ r113
r113
← 0x10 (INV)
OFZ
IFZ
INV
OVF
UNF
INX
DBZ
0
1
2
3
4
5
6
7
31
00
SEE ALSO
fdiv faddflags readpcsw
fdivflags