
Philips Semiconductors
Endian-ness
PRODUCT SPECIFICATION
C-7
The Table C-5 shows the byte-swap implementation of
various pixel formats used in the ICP unit. Refer to Figure
C-2 and Figure C-10 for the byte-swap code used in Ta-
ble C-4 and Table C-5. Byte-swapping is performed only
in Big Endian mode. No swapping is done in the Little En-
dian mode.
The ICP has a byte sex bit (L) defined in its MMIO-based
configuration register. The setting of this bit and the BSX
bit in the PCSW register should be the same. The L bit
must be set by the software.
C.4.5
Video In (VI) and Video Out (VO) Units
The VI unit stores the YUV pixels in planar 4:2:2 or 4:2:0
image format as shown in Figure C-3 and stores the raw
8- and 10-bit data as shown in Figure C-12.
The VO unit uses YUV-4:2:2 planar, YUV-4:2:0 planar,
and YUV-4:2:2+
α packed as input pixel formats. The pla-
nar memory image format of the YUV-4:2:2 and YUV-
4:2:0 are shown in Figure C-3. The YUV-4:2:2+
α memo-
ry image format for overlay is pictured in Figure C-6.
The VI and VO units have a byte-sex bit (Little Endian
and LTL_END) defined in the control MMIO registers,
VI_CONTROL and VO_CONTROL. The definition of
these byte-sex bits and the BSX bit in the PCSW register
should be treated as same. Little Endian and LTL_END
bits must be set by software.
C.4.6
Audio In (AI), Audio-Out (AO), and
SPDIF Out (SDO) Units
The AI unit uses 8-bit mono, 8-bit stereo, 16-bit mono
and 16-bit stereo data. The AO unit uses 16-bit mono,
16-bit stereo, 32-bit mono and 32-bit stereo data. The
SPDO unit uses 32-bit word data. The memory image
format of these data is presented in Figure C-13.
Swapping takes place at the byte level and the bits within
a byte are never disturbed. Both the AI and AO units
have a byte sex bit (LITTLE_ENDIAN) defined in each
units MMIO-based configuration register. The definition
of the these bits and the BSX bit in the PCSW register
should be treated as same. This byte sex bit must be set
by the software.
C.4.7
Variable Length Encoder (VLD) Unit
The VLD inputs data from SDRAM in the form of a bit-
stream with a byte-aligned starting address and outputs
a header stream and a ‘run-level’ data stream. The VLD
unit has a byte sex bit (LITTLE_ENDIAN) defined in its
MMIO-based configuration register. The definition of this
Table C-5. ICP byte swapping type for input data
Endian-ness
L bit
Pixel Type
Swap Type
(see Figure C-2
& Figure C-10)
Big Endian
0
Y,U,V planar
No swap
Big Endian
0
RGB 24+
α
BSW
Big Endian
0
YUV-4:2:2+
α
BSH
Big Endian
0
RGB 15+
α
BSH
Table C-6. ICP byte swapping type for output data
Endian-
ness
L bit
Pixel Type
Swap Type
(see Figure C-2 &
Figure C-10)
Big Endian
0
RGB 8A: 233
No swap
Big Endian
0
RGB 8R: 332
No swap
Big Endian
0
RGB 15+
α
BSH
Big Endian
0
RGB 16
BSH
Big Endian
0
RGB 24+
α
BSW
Big Endian
0
RGB24
packed
No support for Big
Endian
Big Endian
0
YUV- 4:2:2
packed
BSH
Figure C-12. Memory image format for raw 8-bit and 10-bit data
Dn+3
Dn+2
Dn+1
Dn
Big Endian Mode
Little Endian Mode
A+3
A+2
A+1
A+0
A+2
A+1
A+0
raw 8-bit data
in memory
Dn+3
Dn+2
Dn+1
Dn
A+3
A+2
A+1
A+0
A+2
A+1
A+0
raw 10-bit data
in memory
Dn+1
Dn
lsb
msb
lsb
Dn+1
Dn
lsb
msb
lsb
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy
and A+3 corresponds to byte-3 lane of SDRAM/Hwy
lsb is the Least Signicant Byte
msb is the Most Signicant Byte