
Philips Semiconductors
Endian-ness
PRODUCT SPECIFICATION
C-3
C.4.2
Instruction Cache
It is assumed that the instruction cache always operates
in Little Endian regardless of the host and TM1300 endi-
an-ness. Instruction cache does not use the PCSW’s
byte sex bit (BSX). The compiler supports the loading of
instructions in memory differently for Big Endian and Lit-
tle Endian modes.
C.4.3
TM1300 PCI Interface Unit
The TM1300 highway bus and the PCI bus are address
invariant buses, i.e. a data corresponding to address
zero is always transferred through the byte-zero line re-
gardless of the endian-ness. The address-invariant na-
ture of the PCI and the highway buses allows data to be
transferred from/to PCI bus directly to/from SDRAM with-
out byte swapping in either Big or Little Endian mode The
byte swapping of data for Big Endian mode is performed
by the data cache unit. However, MMIO data does not go
through the byte swapper in the Data cache. This results
in using a byte-swapper in the BIU to byte-swap the
MMIO data in Big Endian mode.
The TM1300 BIU has a separate byte sex (SE, Swap En-
abled) flag defined in its control register (BIU_CTL). This
byte-sex flag must be set by the software, i.e. MMIO
write operation from the host CPU. This byte-sex flag is
used only for MMIO data accesses and none of the
MMIO data accesses is affected by this SE flag. Table C-
4 shows the byte-swap logic that handles the MMIO ac-
cesses from the DSPCPU and host CPU and the non
MMIO data accesses from any source.
The BIU has several special registers to handle memory,
PCI configuration, I/O and DMA accesses. It does not
byte-swap the I/O data from the special registers.
The
data cache and software performs the necessary byte
swapping for this data.
When using TM1300 in Little Endian-based systems, the
first transaction to the TM1300 is to set the SE bit in the
BIU configuration register to avoid unnecessary software
byte-swapping in the host CPU for the subsequent MMIO
read/write accesses. The SE bit in the BIU_CTL register
controls the byte swapping of outgoing and incoming
data from PCI bus. The default value of SE is ‘0’, i.e the
BIU byte-swaps the MMIO data including the write oper-
ation to the BIU_CTL register. Software is required to
byte swap the BIU_CTL register value within the host
CPU before storing the value in BIU_CTL register. Once,
the BIU.SE bit has been set, no additional software byte-
swapping is required for further read/write operations to
any MMIO registers.
C.4.4
Image Coprocessor (ICP)
The input source data for the ICP unit might come from
different units such as Video In, the DSPCPU, PCI bus,
etc. via SDRAM. Data consistency needs to be main-
tained when the TM1300 operates in Little or Big Endian
systems/mode. The ICP needs the capability to operate
on the SDRAM as source data and SDRAM or PCI as
destination data in either Little or Big Endian mode. Fig-
ure C-3, Figure C-4, Figure C-5 and Figure C-6 illustrate
the Big and Little Endian memory image format for the
image input format (Figure C-3) and the three supported
image overlay formats.
The ICP can output the data to either the SDRAM or PCI
bus. RGB 8R and RGB 8A pixel formats are byte
streams and therefore do not require any byte swapping.
Figure C-9 pictures the data format. RGB-24
+α, RGB-
15
+α, RGB-16 and YUV-4:2:2 pixel formats can be used
to output the pixels to PCI or SDRAM in both Endian
modes. Output formats are shown, respectively, in Fig-
ure C-4, Figure C-5, Figure C-8, and Figure C-7. Packed
RGB-24 cannot be used in Big Endian mode. Little Endi-
an data format is shown in Figure C-11.
Table C-3. Big Endian data format in the TM1300 DSPCPU register, highway, SDRAM memory, PCI bus, host
memory, and host CPU register
PCSW-
BSX
value
Endian
Mode
Data transaction
type
Address
Data in
DSPCPU
register
msb lsb
Data in highway/
Dcache/SDRAM/
PCI-bus
byte3
byte0
[31:24]
[7:0]
Data in Host
CPU register
msb
lsb
Data in host
memory
byte0
byte3
[31:24]
[7:0]
0
Big
Word r/w
00001000
01020304
04030201
01020304
0
Big
Half-word r/w
00001000
xxxx0304
xxxx0403
xxxx0304
0304xxxx
0
Big
Half-word r/w
00001002
xxxx0304
0403xxxx
xxxx0304
0
Big
Byte read/write
00001000
xxxxxx04
04xxxxxx
0
Big
Byte read/write
00001001
xxxxxx04
xxxx04xx
xxxxxx04
xx04xxxx
0
Big
Byte read/write
00001002
xxxxxx04
xx04xxxx
xxxxxx04
xxxx04xx
0
Big
Byte read/write
00001003
xxxxxx04
04xxxxxx
xxxxxx04
Table C-4. BIU.SE bit usage in processing data in
BIU unit
BIU.SE
value
Endian
Mode
MMIO
access
from
DSPCPU
MMIO
access from
PCI side
Non MMIO
data
0
Big
No byte-swap
byte-swap
No byte-
swap
1
Little
No byte-swap
No byte-
swap