
TM1300 Data Book
Philips Semiconductors
3-14
PRODUCT SPECIFICATION
3.9.2
Data Breakpoints
The data-breakpoint address-range and compare-value
registers are shown in Figure 3-13. After RESET, the val-
ue of the data breakpoint registers is undefined. (MMIO-
register addresses shown are offset with respect to
MMIO_BASE.)
The data-breakpoint control register is shown in
Figure 3-14. On RESET, the BDCTL register is cleared.
(The register address shown is offset with respect to
MMIO_BASE.)
When the DC bits in the data breakpoint control register
are not set to ‘0’, data breakpoints are activated. When
the value of the DC bits is ‘1’ or ‘3’, any data address from
load operations (if the BL bit is set) and/or store opera-
tions (if the BS bit is set) issued by the DSPCPU is com-
pared against the low and high address-range values.
The DAC bit in the breakpoint control register determines
whether data addresses need to be inside or outside of
the range defined by the low and high address-range
registers. A successful comparison occurs when either:
DAC = ‘0’ and low
≤ daddr ≤ high, or
DAC = ‘1’ and daddr < low or daddr > high.
Note that this comparison works for all addresses re-
gardless of the aperture to which they belong. When the
value of the DC bits is ‘2’ or ‘3’, any data value from load
operations (if the BL bit is set) and/or store operations (if
the BS bit is set) issued by the TM1300 CPU is compared
against the value in the BDATAVAL register. Only the
bits for which the corresponding BDATAMASK register
bits are set to ‘1’ will be used in the comparison. The
DVC bit in the breakpoint control register determines
whether the data value needs to be equal or not equal to
the comparison value. A successful comparison occurs
when either of the following are true:
DVC = ‘0’ and (data & BDATAMASK) = (BDATAVAL &
BDATAMASK).
DVC = ‘1’ and (data & BDATAMASK) != (BDATAVAL &
BDATAMASK).
Address Range Start
BINSTLOW (r/w)
0x10 1004
31
0
MMIO_BASE
offset:
BINSTHIGH (r/w)
0x10 1008
3
7
11
15
19
23
27
Address Range End
Figure 3-12. Instruction-breakpoint address-range registers.
BDATAALOW (r/w)
0x10 1030
31
0
MMIO_BASE
offset:
BDATAAHIGH (r/w)
0x10 1034
BDATAVAL (r/w)
0x10 1038
BDATAMASK (r/w)
0x10 103C
Address Range Start
3
7
11
15
19
23
27
Address Range End
Data Breakpoint Value
Data Breakpoint Value Mask
Figure 3-13. Data-breakpoint address-range and value-compare registers.
31
0
MMIO_BASE
offset:
BDCTL (r/w)
0x10 1020
3
7
11
15
19
23
27
‘DVC’ Data Value Control:
0
Breakpoint if data equal
1
Breakpoint if data not equal
DC
BS BL
‘BS’ Break on Store:
0
Don’t check data stores
1
Do check data stores
‘DAC’ Data Address Control:
0
Breakpoint if address inside range
1
Breakpoint if address outside range
‘BL’ Break on Load:
0
Don’t check data loads
1
Do check data loads
‘DC’ Data Control:
0
No checking
1
Check data addresses
2
Check data values
3
Check data value and addresses
Figure 3-14. Data-breakpoint control register.