
TM1300 Data Book
Philips Semiconductors
1-16
PRODUCT SPECIFICATION
1.9.4.9
JTAG I/O timing
Notes:
1. See the timing measurement conditions in Figure 1-10.
2. See the timing measurement conditions in Figure 1-9.
1.9.4.10
I2C I/O timing
Notes:
1. See the timing measurement conditions in Figure 1-11.
2. See the timing measurement conditions in Figure 1-12.
3. See the timing measurement conditions in Figure 1-13.
4. See the timing measurement conditions in Figure 1-14.
5. See the timing measurement conditions in Figure 1-15.
1.9.4.11
Video In I/O Timing
Notes:
1. See the timing measurement conditions in Figure 1-16.
1.9.4.12
Video Out I/O Timing
Notes:
1. See the timing measurement conditions in Figure 1-17.
2. See the timing measurement conditions in Figure 1-18.
3. CLKOUT asserted, i.e. the VO unit is the source of VO_CLK
4. CLKOUT negated, i.e. the external world is the source of VO_CLK
Symbol
Parameter
Min.
Max
Units
Notes
fJTAG-CLK
JTAG clock frequency
20
MHz
Tclk-TDO
JTAG_TCK to JTAG_TDO valid delay
2
10
ns
1
Tsu-TCK
Input setup time to JTAG_TCK
3
ns
2
Th-TCK
Input hold time from JTAG_TCK
7
ns
2
Symbol
Parameter
Min.
Max
Units
Notes
fSCL
SCL clock frequency
400
kHz
1
TBUF
Bus free time
1
us
2
Tsu-STA
Start condition set up time
1
us
3
Th-STA
Start condition hold time
1
us
3
TLOW
SCL LOW time
1
us
1
THIGH
SCL HIGH time
1
us
1
Tf
SCL and SDA fall time (Cb = 10-400 pF, from VIH-IIC to VIL-IIC)
20+0.1Cb
250
ns
1
Tsu-SDA
Data setup time
100
ns
4
Th-SDA
Data hold time
0
ns
4
Tdv-SDA
SCL LOW to data out valid
0.5
us
5
Tdv-STO
SCL HIGH to data out
1
ns
5
Symbol
Parameter
Min.
Max
Units
Notes
fVI-CLK
Video In clock frequency
81
MHz
Tsu-CLK
Input setup time to VI_CLK
2
ns
1
Th-CLK
Input hold time from VI_CLK
2
ns
1
Symbol
Parameter
Min.
Max
Units
Notes
fVO-CLK
Video Out clock frequency
81
MHz
TCLK-DV
VO_CLK to VO_DATA (or VO_IO*) out
3
8.5
ns
1,3
TCLK-DV
VO_CLK to VO_DATA (or VO_IO*) out
3
8.5
ns
1,4
Tsu-CLK
VO_IO* setup time to VO_CLK
10
ns
2
Th-CLK
VO_IO* hold time from VO_CLK
3
ns
2