參數(shù)資料
型號(hào)： XRT82L24IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 9/43頁(yè)
文件大?。?/td> 285K
代理商： XRT82L24IV
á
XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
7
18
RDY_DTACK
O
Ready Output (Data Transfer Acknowledge Output)
.
With Intel bus timing, RDY is asserted "High" to indicate the device has com-
pleted a read or write operation. When configured in Motorola bus timing,
DTACK is asserted Low to indicate the device has completed a read or write
cycle.
67
68
69
70
A[3]
A[2]
A[1]
A[0]
I
Host Mode, Microprocessor Interface Address Bus [3]
Host Mode, Microprocessor Interface Address Bus [2]
Host Mode, Microprocessor Interface Address Bus [1]
Host Mode, Microprocessor Interface Address Bus [0].
56
57
58
59
60
61
62
63
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
I/O
Data Bus[7:0]
.
Microprocessor read/write data bus pins.
CLOCKS
66
MCLK
I
Master Clock Input
.
This signal is an independent 2.048MHz clock with accuracy better than
±50ppm and duty cycle within 40% to 60%. The function of MCLK is to provide
internal timing for the PLL clock recovery circuit, jitter attenuator block, refer-
ence clock during transmit all ones data and timing reference for the micropro-
cessor in Host Mode operation.
If
MClk
is absent, all receive channels perform as analog front-end (AFE). The
OR-ed
RZ
data is also available at
RxClk
output in this mode, instead. The
clock recovery function is disabled.
JITTER ATTENUATOR
56
TXJA
I
Transmit Jitter Attenuator Select
.
In Hardware Mode, connect this pin “High” to select jitter attenuator in the trans-
mit path and connect Low to disable jitter attenuator.
Setting RXJA simultaneously "High" also disables jitter attenuator selection.
57
RXJA
I
Receive Jitter Attenuator Select
.
In Hardware Mode, connect this pin “High” to select jitter attenuator in the
receive path and connect Low to disable jitter attenuator.
Setting TXJA simultaneously "High" also disables jitter attenuator selection.
CONTROL
8
SR/DR
I
Single rail/Dual Rail Control:
Hardware Mode
Connect this pin “Low” to select transmit and receive data format in dual-rail
mode. In this mode, HDB3 encoder and decoder are not available. Connect this
pin "High" to select single-rail data format.
N
OTE
:
Internally pulled -down with a 50k
resistor.
10
Codes
I
Coding/Decoding Select
.
In Hardware Mode
, if single-rail data format is selected (pin 8 =”1”), connect
this pin "High" to select AMI encoding and decoding. Connect this pin Low to
select HDB3.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料
PDF描述
XRT82L24 Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時(shí)鐘恢復(fù)和振動(dòng)衰減器）)
XRT82L34 Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）)
XRT82L38 Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）)
XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
XRT83D10IW SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT82L34IV 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
XRT83D10 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
XRT83D10ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83D10IW 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83D10IW-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*