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參數(shù)資料
| 型號： | XRT82L24IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XRT82L24IV |
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XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
11
Degraded Type of Loss of Signal Event (Non-Zero
Amplitude)
If the XRT 82L24 experiences a degraded type of
LOS event (e.g., where there is still a small amount of
discernible signal amplitude in the line signal, but
small enough to qualify as an LOS event) then the
Clock Recovery PLL could lock onto this degraded
line signal and will subsequently drive the same fre-
quency via the RxClk output pins.
CONDITIONS FOR DECLARING AND CLEARING
LOS IN THE E1 MODE.
Each E1 channel of the XRT 82L24 has two criteria
for LOS Detection,
Analog
and
Digital
. A channel will
declare a LOS condition when both of these LOS De-
tectors detect an LOS condition.
Analog LOS Detector
The Analog LOS Detector will declare an LOS condi-
tion, if it determines that the amplitude of the incom-
ing line signal has dropped to less than
-15dB (below the nominal pulse amplitude of 3V for
twisted-pair
, or 2.37V for
coaxial-cable
) for at least
32 bit-periods.
The Analog LOS Detector will clear the LOS condi-
tion, if it determines that the incoming line signal is no
more than 12.5dB below the nominal 3V pulse ampli-
tude.
N
OTE
:
The difference in the signal level required to declare
and clear LOS is 2.5dB. This 2.5dB hysteresis is designed
into the Analog LOS Detector circuitry, in order to prevent
chattering in the LOS output pin or bit-field.
Digital LOS Detector
The Digital LOS Detector will declare an LOS condi-
tion, if it detects a string of at least 32 consecutive
"0"s.
The Digital LOS Detector will clear the LOS condition,
if it determines that the incoming E1 line signal has a
pulse density of 12.5% or more without 16 consecu-
tive “0’s” for at least 32 consecutive bit periods.
N
OTE
:
The pulse density requirement of 12.5% accounts
for HDB3 coding.
RECEIVE DATA MUTING
The XRT 82L24 permits the user to “MUTE” the re-
covered data output signals anytime the LOS condi-
tion is declared. If the user invokes this function, then
the RPOS/RDAT and RNEG output pins will be pulled
to GND for the duration that the LOS condition exists.
This feature is useful in that it prevents the LIU from
routing electrical noise (which has been “recovered”
by the Clock Recovery PLL) to the Framer IC and pre-
venting it from declaring an LOS condition. This fea-
ture is enabled by setting the RXMUTE bit to a “1” in
the Host Mode (Register 1, Bit 2 Location) or by con-
necting pin 67 High in the Hardware Mode.
LOOP-BACK MODES
Each channel within the XRT 82L24 can be config-
ured to operate in any of the following loop-back
modes:
Remote Loop-Back Mode
Digital Local Loop-Back Mode
Analog Local Loop-Back Mode
Each of these loop-back modes are described in
some detail below.
REMOTE LOOP-BACK (RLOOP) MODE
With Remote Loop-Back activated, (Channel Control
Register bit 2 = “1”) in Host Mode or in Hardware
Mode with
LoopSEL
(pin 58) tied Low and
LoopEN
tied High received data after the jitter attenuator (if
selected) is looped back to the transmit path using
RxClk as transmit timing. In this mode the data/sig-
nals applied to the TxClk, TPOS/TDAT and TNEG in-
put pins are ignored, while RxClk and received data
will continue to be available at their respective output
pins. Simultaneously setting RLOOP and ALOOP ac-
tive is not allowed (see Loop-Back Mode in Figure 4 &
Figure 5). Remote loop-back has priority over TAOS.
DIGITAL LOCAL LOOP-BACK (DLOOP) MODE
The Digital Local Loop-Back mode allows the trans-
mit clock and data to be looped back to the corre-
sponding receiver output pins through the encoder/
decoder and the jitter attenuator. In this mode, the re-
ceive line signal is ignored, but the transmit data will
be sent to the line uninterrupted. This loop back fea-
ture allows users to configure the line interface as a
pure jitter attenuator. (see Loop-Back Mode in
Figure 6 & Figure 7).
N
OTE
:
Digital Local Loop-Back is not supported in Hard-
ware Mode.
ANALOG LOCAL LOOP-BACK (ALOOP) MODE
With Analog Local Loop-Back activated, the transmit
data at TTIP and TRING are looped-back to the ana-
log input of the receiver. External inputs at RTIP/
RRING in this mode are ignored while valid transmit
data continues to be sent to the line. Analog Loop-
Back exercises most of the functional blocks of the
line interface (see Loop-Back Mode in Figure 8 &
Figure 9).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT82L24 | Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時鐘恢復(fù)和振動衰減器）) |
| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| XRT83D10 | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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