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參數(shù)資料
| 型號： | XRT82L24IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 10/43頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XRT82L24IV |
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XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
á
8
19
INT
O
Interrupt Output
.
This pin is asserted Low to indicate an alarm condition has occurred within the
device. Interrupt generation can be globally disabled by setting the GIE bit to a
"0" in the command control register.
N
OTE
:
This pin is an open drain output and requires an external 10K
pull-up
resistor.
20
ICT
I
In-Circuit Testing (Active Low)
.
When this pin is tied Low, all output pins are forced to high impedance state for
in-circuit testing.
N
OTE
:
Internally pulled -up with 50k
.
58
LOOPSEL
I
DLoop-back Mode Select
.
In Hardware Mode, if LOOPEN_(0-3) is “High”, this pin is used for selecting
loop-back mode. Connect this pin "High" to select local loop-back and Low to
select remote loop-back. Digital Loop-back is not supported in Hardware Mode.
62
61
60
59
LOOPEN_0
LOOPEN_1
LOOPEN_2
LOOPEN_3
I
Loop-back Enable - Channel_n:
In Hardware Mode
:
Connect this pin “High” to enable channel_n loop-back operation. Remote or
local loop-back is determined by pin 58 setting.
63
FIFOS
I
FIFO Size Select.
In Hardware Mode, connect this pin "High" selects 64 bit FIFO depth and con-
nect Low to select 32 bit FIFO depth.
POWER SUPPLIES AND GROUNDS
12
AVDD
****
Analog Positive Supply(3.3V± 5%)
28
DVDD
****
Digital Positive Supply(3.3V± 5%)
33
DVDD
****
Digital Positive Supply(3.3V± 5%)
90
36
40
86
TVDD_0
TVDD_1
TVDD_2
TVDD_3
****
Transmitter_n Analog Positive Supply(3.3V± 5%).
43
AVDD
****
Analog Positive Supply(3.3V± 5%)
48
DVDD
****
Digital Positive Supply(3.3V± 5%)
64
DVDD
****
Digital Positive Supply(3.3V± 5%)
78
DVDD
****
Digital Positive Supply(3.3V± 5%)
11
AGND
****
Analog Ground
13
DGND
****
Digital Ground
29
DGND
****
Digital Ground
30
DGND
****
Digital Ground
92
34
42
84
TGND_0
TGND_1
TGND_2
TGND_3
****
Transmitter_n Analog Ground.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT82L24 | Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時鐘恢復(fù)和振動衰減器）) |
| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
| XRT83D10 | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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