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參數(shù)資料
| 型號： | XRT82L24IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 12/43頁 |
| 文件大?。?/td> | 285K |
| 代理商： | XRT82L24IV |
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XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
á
10
SYSTEM-FUNCTIONAL DESCRIPTION
A simplified single channel block diagram of the XRT
82L24 is presented in Figure 1. The XRT 82L24 con-
sists of four identical transmit and receive channels
for E1(2.048 Mbps) PCM systems. The operational
mode of each channel of the line interface can be
configured by the microprocessor interface (Host
Mode) or by Hardware control.
RECEIVER
At the receiver input, cable attenuated AMI signals
can be coupled to the receiver using a capacitor or a
1:2 transformer. The receive signal first goes through
the equalizer for signal conditioning before being ap-
plied to the data recovery circuit. The data recovery
circuit includes a peak detector which is set typically
at 50% for E1 of the equalizer output peak amplitude
for data slicing. After the data slicers, the digital rep-
resentation of the AMI signals goes to the clock re-
covery circuit for timing recovery and subsequently to
the HDB3 decoder (if selected) before they are output
via the RxPOS/RDATA and RxNEG/LCV pins. The
digital data output can be in dual-rail or single-rail
mode depending on the option selected. Clock and
timing recovery is accomplished by means of a digital
PLL scheme which can tolerate high input jitter and
meets or exceeds the jitter tolerance requirements as
specified in the ITU - G.823 standard.
JITTER ATTENUATOR
To reduce jitter in the transmit line signal or recovered
clock and data signals, a crystal-less jitter attenuator
with a 32x2 bit or 64x2 bit FIFO is provided for each
channel. The jitter attenuator can be configured to op-
erate in either the transmit or receive path, or it can
be disabled through Host or Hardware Mode control.
The jitter attenuator design is based on a digital
scheme that uses the MCLK signal as a reference in-
put. No other high frequency clock is necessary. With
the jitter attenuator selected, the typical throughput
delay is 16 bits for a 32 bit FIFO depth or 32 bit for a
64 bit FIFO depth. The design of the jitter attenuator
is such that if the write and read pointers of the FIFO
are within two bits of overflowing or underflowing, the
bandwidth of the jitter attenuator is automatically wid-
ened in order to permit the “Jitter Attenuator” PLL to
track the short term input jitter to avoid data corrup-
tion. When this situation occurs, the jitter attenuator
will not attenuate input jitter until the read/write point-
er's position is outside the two bit window. Under nor-
mal condition, the jitter transfer characteristic meets
the narrow bandwidth requirement as specified in
ITU- G.736 and ITU- I.431standards.
HDB3/AMI DECODER
The decoder function is only active if the chip has
been configured to operate in the single-rail mode.
When the single-rail mode is selected, the receive
line signal will be decoded according to HDB3 rules
for E1. Further, any bipolar violation of the HDB3 line
coding scheme will be flagged as a Line Code Viola-
tion via the LCV output pin. The LCV output pin will
be pulsed high for one RxClk cycle for each line code
violation that is detected. Excessive number of zeros
in the receive data stream are also flagged as a line
code violation via the same output pin. If AMI decod-
ing is selected in single-rail mode operation, every bi-
polar violation in the receive data stream is reported
as error at the LCV pin.
RECEIVER LOSS OF SIGNAL (LOS)
The receiver loss of signal monitoring function is im-
plemented using both analog and digital detection
schemes compatible with ITU G.775 requirements.
When the amplitude of the E1 line signal at RTIP/
RRING drops 16dB (typical) below the 0dB nominal
level the digital circuit is activated to parse through
and check for 32 consecutive zeros before LOS is as-
serted, to indicate loss of input signal. The number of
consecutive zeros before LOS is declared can be in-
creased to 4096 bits. During extended LOS Mode,
the LOS condition will be cleared when 4096 more
valid data bits are present (when operating in the
Host Mode). The LOS condition is cleared when the
input signal rises above 16dB below 0dB nominal lev-
el and meets 12.5% density of 4 ones in a 32 bit win-
dow with no more than 16 consecutive zeros.
Clock signals generated when LOS is declared
The output signal at the RxClk output pin depends
upon the type of LOS condition that is occurring.
Complete Loss of Signal (Zero Amplitude)
If the XRT 82L24 experiences a complete Loss of
Signal (e.g., no signal amplitude), then the XRT
82L24 Clock Recovery PLL enters the Training Mode,
and Differentially begins to lock onto the signal ap-
plied to the MCLK input pin. As a consequence, the
Clock Recovery PLL will begin to drive a clock signal
to the Terminal Equipment (via the RxClk output pin),
which is derived from the MCLK input pin.
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| XRT82L24 | Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時鐘恢復(fù)和振動衰減器）) |
| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復(fù)和振蕩衰減器）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| XRT83D10IW-F | 功能描述:外圍驅(qū)動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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