參數(shù)資料
型號(hào)： XRT82L24IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁(yè)數(shù)： 7/43頁(yè)
文件大?。?/td> 285K
代理商： XRT82L24IV
á
XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
5
5
21
55
71
TxClk_0
TxClk_1
TxClk_2
TxClk_3
I
Transmitter_n Clock Input: E1 rate at 2.048MHz ± 50ppm.
During normal operation both in Host Mode and Hardware Mode,
TxClk
is used
for sampling input data at
TxPOS
/
TData
and
TxNEG
, while
MCLK
is used as
the timing reference for the transmit pulse shaping circuit. If
TxClk
is active
while
MClk
is not present,
TxPOS
and
TxNEG
accepts NRZ data input and the
transmit pulse width is determined by
TxClk
clock duty cycle. If
TxClk
is tied to
“Low”,
TxPOS
and
TxNEG
input accepts
RZ
data format and the pulse width is
determined by the duty cycle of the input data. In
RZ
Mode, single-rail data for-
mat is not supported.
In Hardware Mode,
if TxClk is tied "High" for more than 10 μs, then TAOS (a
continuous all one's AMI signal) will be transmitted to the line using
MCLK
as
timing reference.
If TxClk_0 is tied “Low” for more than 10 μs, the transmitter will be powered
down and the output will be tri-stated.
14
15
16
17
TxOFF_0
TxOFF_1
TxOFF_2
TxOFF_3
I
Powered-down Transmitter_n:
In Hardware Mode, tie this pin "High" to power-down channel 0 transmitter and
set TTIP_n and TRing_n to high impedance.
N
OTE
:
Internally pulled -up with a 50k
resistor.
91
35
41
85
TRing_0
TRing_1
TRing_2
TRing_3
O
Transmitter_n Ring Output:
Negative Differential data output to the line.
89
37
39
87
TTIP_0
TTIP_1
TTIP_2
TTIP_3
O
Transmitter_n Tip Output:
Positive Differential data output to the line.
MICROPROCESSOR INTERFACE
6
RESET
I
Hardware Reset
(Active Low). When this pin is tied Low for more than 10
μ
S,
the device is put in the reset state.
N
OTE
:
Internally pulled -up with a 50k
resistor.
7
PTS1
ClkE
I
I
Processor Type Select bit 1:
Host Mode
In Host Mode the appropriate bits are set in the command mode
Hardware Mode:
The state of the ClkE input controls the sampling edge of both TxClk and RxClk.
A “1” selects the positive edge of TxClk and RxClk
A “0” selects the negative edge of TxClk and RxClk.
PIN DESCRIPTIONS
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
8HC11,8081,80C188 (async.)
Motorola 68K (async.)
Intel x86 (sync.)
Intel i906,Motorola 860 (sync.)
PTS1
0
1
0
1
PTS2
0
0
1
1
相關(guān)PDF資料
PDF描述
XRT82L24 Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時(shí)鐘恢復(fù)和振動(dòng)衰減器）)
XRT82L34 Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）)
XRT82L38 Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）)
XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
XRT83D10IW SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT82L34IV 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
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XRT83D10IW 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83D10IW-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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