參數(shù)資料
型號： XRT82L24IV
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
文件頁數(shù)： 18/43頁
文件大?。?/td> 285K
代理商： XRT82L24IV
XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
á
16
TRANSMIT PULSE SHAPER
The transmit pulse shaper uses high a speed clock
derived from MCLK to synthesize the shape and
width of the transmitted pulse applied to TTIP and
TRING. The internal high speed timing generator
eliminates the need for a tightly controlled transmit
clock TxClk duty cycle.
The intrinsic jitter at the transmit output using a jitter-
free input clock source and with the jitter attenuator
disabled will generate no more than 0.03UIpp.
DRIVER MONITOR
The driver monitor circuit is used for detecting trans-
mit driver failure by monitoring the activity at TTIP
and TRING. Driver failure may be caused by a short-
circuit in the primary of the transformer or system
problems at the input.
In the Host Mode, when the driver monitor detects no
transitions at TTIP and TRING for more than 128
clock cycles, the DMO bit (bit 7) in the interface regis-
ter is set and results in an interrupt (INT) to be gener-
ated. Driver monitor function is not supported in
Hardware Mode.
TxPOS/TDATA and TxNEG Polarity
In HOST Mode, transmit data at TxPOS/TDATA and
TxNEG can be configured for active Low or active
High operation, by controlling the state of the DATAP
bit in the interface register. Writing a "0" to this bit se-
lects active High data and a "1" selects active Low da-
ta. This control bit also selects receive output data
polarity (see Receive Data Invert Mode description).
This feature is not supported in Hardware Mode.
TRANSMIT OFF CONTROL
Each transmit channel of the line interface can be
shut down by writing a "1" to TxOFF in the channel
control interface register. In the “Transmitter off”
mode, the entire transmitter is disabled and the out-
puts at TTIP and TRING are placed in a high imped-
ance state. In Hardware Mode, pins 14 through pin 17
are used for powering down each transmit channel in-
dependently.
INTERFACING THE XRT 82L24 TO THE LINE
The XRT 82L24 in E1 configuration can be transform-
er coupled to 75
coaxial or 120
twisted pair lines
as shown in Figure 12 and Figure 13 below.
F
IGURE
12. XRT 82L24 C
HANNEL
1
IN
AN
E1
UNBALANCED
75
APPLICATION
TTIP_0
TRing_0
RTIP_0
RRing_0
TxPOS
TxNEG
TxLineClk
RxPOS
RxNEG
RxLineClk
Loss of signal
4
3
5
100
99
1
2
89
91
94
95
TPOS_0
TNEG_0
TClk_0
RPOS_0
RNEG_0
RClk_0
RLOS_0
XRT82L24
R2
9.1
R1
9.1
R3
18.7
1 : 2
T2
T1
BNC
BNC
1
4
5
8
5
8
1
4
1 : 2
1
2
1
2
Coaxial
Cable
Coaxial
Cable
相關PDF資料
PDF描述
XRT82L24 Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時鐘恢復和振動衰減器）)
XRT82L34 Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）)
XRT82L38 Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）)
XRT83D10 SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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相關代理商/技術參數(shù)
參數(shù)描述
XRT82L34IV 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
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XRT83D10IW 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83D10IW-F 功能描述:外圍驅動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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