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參數(shù)資料
| 型號： | XRT82L24IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 16/43頁 |
| 文件大小： | 285K |
| 代理商： | XRT82L24IV |
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XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
á
14
RESET OPERATION
The XRT 82L24 provides both Hardware and Soft-
ware resets. In Hardware reset, with pin 6 forced to
"0" for more than 10μs, the entire state of the device
including the microprocessor R/W registers are reset.
In Software reset, only the state of the interface is re-
set (the microprocessor registers are not affected).
RECEIVER MODES OF OPERATION
Through the microprocessor interface or in Hardware
Mode, XRT 82L24 offers several alternative receive
modes of operation making it flexible for different ap-
plications as dictated by the system requirements.
RECEIVE DATA INVERT MODE
Receive output data by default is active high at Rx-
POS/RDATA and RxNEG/LCV pins. These signals
can be changed to active Low by setting the DATAP
bit in the interface register(Register 1, Bit 3 = “1”). In
single rail mode DATAP = “1”, (Register 0, Bit 7 = “1”),
LCV output also becomes active Low. Data invert
Mode is only available in Host Mode.
F
IGURE
8. A
NALOG
L
OCAL
L
OOP
-B
ACK
SIGNAL
FLOW
J
ITTER
A
TTENUATOR
SELECTED
&
IN
R
ECEIVE
PATH
Rx
Clock &
Data
Recovery
Decoder
TxPOS
TxNEG
TxClk
RxClk
RxPOS
RxNEG
Tx
Encoder
Timing
Control
TTIP
TRing
RTIP
RRing
JA
F
IGURE
9. A
NALOG
L
OCAL
L
OOP
-B
ACK
SIGNAL
FLOW
J
ITTER
A
TTENUATOR
SELECTED
&
IN
TRANSMIT
PATH
Rx
Clock &
Data
Recovery
Decoder
TxPOS
TxNEG
TxClk
RxClk
RxPOS
RxNEG
Tx
Encoder
Timing
Control
JA
TTIP
TRing
RTIP
RRing
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| XRT82L24 | Quad E1 Line Transceiver with Clock Recovery and Jitter Attenuator(四E1線收發(fā)器（帶時鐘恢復和振動衰減器）) |
| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
| XRT82L38 | Octal E1/T1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(八 T1/E1/J1線收發(fā)器（帶時鐘恢復和振蕩衰減器）) |
| XRT83D10 | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10IW | SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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