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參數(shù)資料
| 型號(hào)： | XRT82L24IV |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 17/43頁 |
| 文件大小： | 285K |
| 代理商： | XRT82L24IV |
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XRT82L24
QUAD E1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.2.3
15
RxClk Clock Sampling Edge
The sampling edge of the RxClk output can be
changed through control bit RClkE within the inter-
face register for receive output data re-timing. With
RClkE=”1”, (Bit 5 = “1”), data is validated on the rising
edge of RxClk and with RClkE=”0”, (Bit 5 = “0”),, re-
ceive data is validated on the falling edge of RxClk. In
Hardware Mode, the state of pin 7 (ClkE) controls the
rising or falling edge of RxClk for data re-timing.
TRANSMIT CLOCK SAMPLING EDGE
NRZ Transmit data at TxPOS/TDATA or TxNEG is
clocked serially into the device using TxClk. With the
interface register bit 4 (TClkE=”1”), input data is sam-
pled on the rising edge of TxClk. The sampling edge
is inverted when TClkE= “0”. In Hardware Mode, the
state of pin 7 (ClkE) controls the sampling edge of
both TxClk and RxClk.
SINGLE RAIL, DUAL RAIL
Transmit data format can be in dual-rail (SR/DR=1) or
single-rail modes (SR/DR=0). In Hardware Mode, du-
al or single-rail format is determined by the state of
pin 8. For single-rail mode operation, NRZ data can
be applied to TxPOS/TDATA with TxClk, while TxNEG
input is left unconnected. The transmitter converts
NRZ input data into differential signal for transmission
to the line using low impedance output drivers.
TRANSMIT ALL ONES (TAOS)
In the Host Mode, individual channels can be pro-
grammed to transmit an all “Ones” AMI signal by set-
ting the per channel bit control TAOS=1. In this mode,
input data at TxPOS/TDATA and TxNEG are ignored.
In Host Mode, reference clock for TAOS is TxClk. If
TxClk is not available, MCLK is used for transmission.
In Hardware Mode, if TxClk is not present and High
for more than 10μs, TAOS is transmitted using MCLK
as a reference. Remote Loop-Back has priority over
TAOS request.
HDB3/AMI ENCODER
The encoder is only available in single-rail mode (SR/
DR=1) in Host Mode, or pin 8 set High in Hardware
Mode. In an E1 system, if interface register
CODES=0, HDB3 encoding is selected. Input data
applied to TxPOS/TDATA which contains more than
four consecutive zeros will be removed and replaced
by “000V” or “B00V”, where "B” indicates a pulse con-
forming with bipolar rule and "V" represents a pulse
violating the rule. With register CODES=”1”, AMI
coding is selected. In Hardware Mode, HDB3 or AMI
coding selection is determined by the state of pin 10.
The choice of these codes is made such that an odd
number of “B” pulses is transmitted between consec-
utive bipolar violation “V” pulses
F
IGURE
10. D
ATA
CHANGES
ON
RISING
EDGE
OF
C
LK
AND
D
ATA
IS
SAMPLED
ON
FALLING
EDGE
Data Sampled
Clk
Data
Data Sampled
F
IGURE
11. D
ATA
CHANGES
ON
FALLING
EDGE
OF
C
LK
AND
IS
SAMPLED
ON
RISING
EDGE
Data Sampled
Clk
Data
Data Sampled
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| XRT82L34 | Quad T1/E1/J1 Line Transceiver with Clock Recovery and Jitter Attenuator(四 T1/E1/J1線收發(fā)器（帶時(shí)鐘恢復(fù)和振蕩衰減器）) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT82L34IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| XRT83D10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT |
| XRT83D10ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 1 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83D10IW-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Single Ch; 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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