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| 型號： | XE8000EV108 |
| 廠商： | Semtech |
| 文件頁數(shù)： | 76/143頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XE8806/XE8807 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | XE88LC06AMI026 |
| 所含物品： | 完全組裝的評估板 |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
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Semtech 2006
www.semtech.com
6-5
XE8806A/XE8807A
6.5.5
BusError reset
The address space is assigned as shown in the register map of the product. If the EnBusError bit in the
RegSysCtrl register is set and the software accesses an unused address, a reset is generated.
6.6
Sleep mode
Entering the sleep mode will reset a part of the circuit. The reset is used to configure the circuit for correct wake-up
after the sleep mode. If the SleepEn bit in the RegSysCtrl register has been set, the sleep mode can be entered
by setting the bit Sleep in RegSysReset. During the sleep mode, the nresetsleep signal is active. For detailed
information on the sleep mode, see the system documentation.
6.7
Control register description and operation
Two registers are dedicated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep,
SleepFlag and SleepEn are also located in those registers and are described in the chapter dedicated to the
different operating modes of the circuit (system block).
The RegSysReset register gives information on the source that generated the last reset. It can be read at the
beginning of the application program to detect if the circuit is recovering from an error or exception condition, or if
the circuit is starting up normally.
when ResetBusError is 1, a forbidden address access generated the reset.
when ResetWD is 1, the watchdog generated the reset.
when ResetfromPortA is 1, a PortA combination generated the reset.
Note: If no bit is set to 1, the reset source was either the NRESET pin or the internal POR.
Note: Several bits might be set or not, if the register was not cleared in between 2 reset occurrences.
The two other bits concern the sleep mode control and information (see system documentation for the sleep mode
description).
When SleepFlag is 1, the sleep mode was active before the reset occurred. This bit will always appear
together with the ResetfromPortA bit since all other possibilities to leave the sleep mode (POR and
NRESET pin) will clear the SleepFlag.
When Sleep is set to 1, and SleepEn is 1, the sleep mode is entered. The bit always reads back a 0.
The RegSysCtrl register enables the different available reset sources and the sleep mode.
EnBusError enables the reset due to a bus error condition.
EnResetWD enables the reset due to the watchdog (can not be disabled once enabled).
EnResetPConf enables the reset of the port configurations when reset by Port A, a Bus Error or the
watchdog.
SleepEn unlocks the Sleep bit. As long as SleepEn is 0, the Sleep bit has no effect.
6.8
Watchdog
The watchdog is a timer, which has to be cleared at least every 2 seconds by the software to prevent a reset to be
generated by the timeout condition.
The watchdog can be enabled by software by setting the EnResetWD bit in the RegSysCtrl register to 1. It can
then only be disabled by a power on reset or by setting the NRESET pin to a low state.
The watchdog timer can be cleared by writing consecutively the values Hx0A and Hx03 to the RegSysWd register.
The sequence must strictly be respected to clear the watchdog.
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