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    參數(shù)資料
    型號: XE8000EV108
    廠商: Semtech
    文件頁數(shù): 7/143頁
    文件大?。?/td> 0K
    描述: EVAL BOARD FOR XE8806/XE8807
    標(biāo)準(zhǔn)包裝: 1
    類型: MCU
    適用于相關(guān)產(chǎn)品: XE88LC06AMI026
    所含物品: 完全組裝的評估板
    產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
    Semtech 2006
    www.semtech.com
    14-24
    XE8806A/XE8807A
    Pattern1
    01000
    0
    Pattern2
    01001
    0
    Pattern3
    01010
    0
    Pattern4
    01011
    0
    Table 14-29. XE1202A register set-up (see XE1202A datasheet for bit explanation)
    14.12.2.4.2
    RF interface set-up
    We then set-up the RF interface of the microcontroller circuit as a receiver (RfifEnRx = 1 and RfifEnTx = 0).
    Assume that the RC clock frequency used in the microcontroller is 1.0 MHz. To select the correct baud rate of 4.8
    kbit/s according to the equation in chapter 14.10 (attention: the baud rate is twice the bit rate in the Manchester
    code), fine*coarse=1.0e06/(16*4.8e3)=13.0. This can be done by setting RfifBRCoarse = 00 and RfifBRFine =
    1100.
    The external bit synchronization clock is switched off by clearing the bit RfifRxClock = 0.
    The decoder is enabled and set to Manchester Level decoding by setting RfifEnCod = 1 and RfifPCM = 011.
    The start detection by protocol violation is enabled by setting RfifEnStart = 01.
    The start sequence detection interrupt is enabled by setting RfifRxIrqEn = 001.
    The set-up of the interface is summarized in the Table 14-30.
    Register
    contents
    RegRfifCmd1
    00000010
    RegRfifCmd2
    10100100
    RegRfifCmd3
    00100010
    Table 14-30. RF interface set-up
    14.12.2.4.3
    Data reception
    In order to handle the received data by interrupt, enable the RF interface reception interrupt in the interrupt handler
    of the circuit.
    Data received before the first start pattern detection after the enabling of the interface are not relevant since we are
    not yet synchronized to the messages. Sine the start detection interrupt has been enabled, nothing has to be done
    until the interrupt occurs.
    When the first interrupt occurs, we are synchronized to the messages. In order to read data in an efficient way, the
    interrupt source is modified and set to “Rx FIFO full” by writing 100 to RfifRxIrqEn. Once this is done, we can wait
    for the next interrupt to download the received message.
    At each new interrupt, we can now read 4 bytes of the received message by reading the register RegRfifRx 4
    consecutive times. The interrupt should be served before the next byte is received since otherwise data may be
    lost by lack of space in the FIFO (overrun error which sets the flag RfifRxFifoOverrun) or because the start
    sequence of the next message is detected which resets the reception FIFO.
    When the complete message is received, the start sequence detection interrupt may be enabled again
    (RfifRxIrqEn = 001) and the sequence starts all over again.
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