參數(shù)資料
型號(hào)： XE8000EV108
廠商： Semtech
文件頁數(shù)： 33/143頁
文件大小： 0K
描述： EVAL BOARD FOR XE8806/XE8807
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC06AMI026
所含物品： 完全組裝的評(píng)估板
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
Semtech 2006
www.semtech.com
17-7
XE8806A/XE8807A
CascadeCD
CountPWM1
Counter C
mode
Counter D
mode
IrqC
source
IrqD
source
PB(1)
function
0
Counter 8b
Downup: C
Counter 8b
Downup: D
Counter
C
Counter
D
PB(1)
1
0
Counter 16b CD
Downup: C
Counter
CD
-
PB(1)
0
1
PWM 8b
Downup: C
Counter 8b
Downup: D
-
Counter
D
PWM C
1
PWM 10 – 16b CD
Downup: C
-
PWM CD
Table 17-13: Operating modes of the counters C and D
17.9
Counter / Timer mode
The counters in counter / timer mode are generally used to generate interrupts after a predefined number of clock
periods applied on the counter clock input.
Each counter can be set individually either in upcount mode by setting CntXDownUp in the register
RegCntConfig1 or in downcount mode by resetting this bit. Counters A and B can be cascaded to behave as a 16
bit counter by setting CascadeAB in the RegCntConfig1 register. Counters C and D can be cascaded by setting
CascadeCD. When cascaded, the up/down count modes of the counters B and D are defined respectively by the
up/down count modes set for the counters A and C.
When in upcount mode, the counter will start incrementing from zero up to the target value which has been written
in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is
generated at the next counter clock pulse and the counter is loaded again with the zero value (Figure 17-2).
When in downcount mode, the counter will start decrementing from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next counter clock pulse and the counter is loaded again with the load value (Figure
17-2).
Be careful to select the counter mode (no capture, not PWM, specify cascaded or not and up or down counting
mode) before writing any target or load value to the RegCntX register(s). This ensures that the counter will start
from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that
both cascaded counters will start from the correct initial values.
The stopping and consecutive starting of a counter in counter mode without a target or load value write operation in
between can generate an interrupt if this counter has been stopped at the zero value (downcount) or at it’s target
value (upcount). This interrupt is additional to the interrupt which has already been generated when the counter
reached the zero or the target value.
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