Table 3-4 shows a short description of the diffe" />
參數(shù)資料
型號： XE8000EV108
廠商： Semtech
文件頁數(shù)： 57/143頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8806/XE8807
標準包裝： 1
類型： MCU
適用于相關產(chǎn)品： XE88LC06AMI026
所含物品： 完全組裝的評估板
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
Semtech 2006
www.semtech.com
3-4
XE8806A/XE8807A
3.3
CPU instruction short reference
Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The notation cc in the
conditional jump instruction refers to the condition description as given in Table 3-6. The notation reg, reg1, reg2,
reg3 refers to one of the CPU internal registers of Table 3-1. The notation eaddr and DM(eaddr) refer to one of the
extended address modes as defined in Table 3-5. The notation DM(xxx) refers to the data memory location with
address xxx.
Instruction
Modification
Operation
Jump addr[15:0]
-,-,-, -
PC := addr[15:0]
Jump ip
-,-,-, -
PC := ip
Jcc addr[15:0]
-,-,-, -
if cc is true then PC := addr[15:0]
Jcc ip
-,-,-, -
if cc is true then PC := ip
Call addr[15:0]
-,-,-, -
STn+1 := STn (n>1); ST1 := PC+1; PC := addr[15:0]
Call ip
-,-,-, -
STn+1 := STn (n>1); ST1 := PC+1; PC := ip
Calls addr[15:0]
-,-,-, -
ip := PC+1; PC := addr[15:0]
Calls ip
-,-,-, -
ip := PC+1; PC := ip
Ret
-,-,-, -
PC := ST1; STn := STn+1 (n>1)
Rets
-,-,-, -
PC := ip
Reti
-,-,-, -
PC := ST1; STn := STn+1 (n>1); GIE :=1
Push
-,-,-, -
PC := PC+1; STn+1 := STn (n>1); ST1 := ip
Pop
-,-,-, -
PC := PC+1; ip := ST1; STn := STn+1 (n>1)
Move reg,#data[7:0]
-,-, Z, a
a := data[7:0]; reg := data[7:0]
Move reg1, reg2
-,-, Z, a
a := reg2; reg1 := reg2
Move reg, eaddr
-,-, Z, a
a := DM(eaddr); reg := DM(eaddr)
Move eaddr, reg
-,-,-, -
DM(eaddr) := reg
Move addr[7:0],#data[7:0]
-,-,-, -
DM(addr[7:0]) := data[7:0]
Cmvd reg1, reg2
-,-, Z, a
a := reg2; if C=0 then reg1 := a;
Cmvd reg, eaddr
-,-, Z, a
a := DM(eaddr); if C=0 then reg := a
Cmvs reg1, reg2
-,-, Z, a
a := reg2; if C=1 then reg1 := a;
Cmvs reg, eaddr
-,-, Z, a
a := DM(eaddr); if C=1 then reg := a
Shl reg1, reg2
C, V, Z, a
a := reg2<<1; a[0] := 0; C := reg2[7]; reg1 := a
Shl reg
C, V, Z, a
a := reg<<1; a[0] := 0; C := reg[7]; reg := a
Shl reg, eaddr
C, V, Z, a
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]; reg := a
Shlc reg1, reg2
C, V, Z, a
a := reg2<<1; a[0] := C; C := reg2[7]; reg1 := a
Shlc reg
C, V, Z, a
a := reg<<1; a[0] := C; C := reg[7]; reg := a
Shlc reg, eaddr
C, V, Z, a
a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7]; reg := a
Shr reg1, reg2
C, V, Z, a
a := reg2>>1; a[7] := 0; C := reg2[0]; reg1 :=a
Shr reg
C, V, Z, a
a := reg>>1; a[7] := 0; C := reg[0]; reg := a
Shr reg, eaddr
C, V, Z, a
a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0]; reg := a
Shrc reg1, reg2
C, V, Z, a
a := reg2>>1; a[7] := C; C := reg2[0]; reg1 := a
Shrc reg
C, V, Z, a
a := reg>>1; a[7] := C; C := reg[0]; reg := a
Shrc reg, eaddr
C, V, Z, a
a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0]; reg := a
Shra reg1, reg2
C, V, Z, a
a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a
Shra reg
C, V, Z, a
a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a
Shra reg, eaddr
C, V, Z, a
a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a
Cpl1 reg1, reg2
-,-, Z, a
a := NOT(reg2); reg1 := a
Cpl1 reg
-,-, Z, a
a := NOT(reg); reg := a
Cpl1 reg, eaddr
-,-, Z, a
a := NOT(DM(eaddr)); reg := a
Cpl2 reg1, reg2
C, V, Z, a
a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a
Cpl2 reg
C, V, Z, a
a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a
Cpl2 reg, eaddr
C, V, Z, a
a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a
Cpl2c reg1, reg2
C, V, Z, a
a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a
Cpl2c reg
C, V, Z, a
a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
Cpl2c reg, eaddr
C, V, Z, a
a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
Inc reg1, reg2
C, V, Z, a
a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a
Inc reg
C, V, Z, a
a := reg+1; if a=0 then C := 1 else C := 0; reg := a
Inc reg, eaddr
C, V, Z, a
a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a
Incc reg1, reg2
C, V, Z, a
a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a
Incc reg
C, V, Z, a
a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
Incc reg, eaddr
C, V, Z, a
a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
Dec reg1, reg2
C, V, Z, a
a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a
相關PDF資料
PDF描述
94SVP476X0020E7 CAP ALUM 47UF 20V 20% SMD
EBC22DRTI-S13 CONN EDGECARD 44POS .100 EXTEND
AT-S-26-8/8/B-14-R MOD CORD STANDARD 8-8 BLACK 14'
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