參數(shù)資料
型號： XE8000EV108
廠商： Semtech
文件頁數(shù)： 34/143頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8806/XE8807
標準包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC06AMI026
所含物品： 完全組裝的評估板
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
Semtech 2006
www.semtech.com
17-8
XE8806A/XE8807A
Figure 17-2. Up and down count interrupt generation.
17.10 PWM mode
The counters can generate PWM signals (Pulse Width Modulation) on the PortB outputs PB(0) and PB(1).
The PWM mode is selected by setting CntPWM1 and CntPWM0 in the RegCntConfig1 register. See Table 17-12
and Table 17-13 for an exact description of how the setting of CntPWM1 and CntPWM0 affects the operating
mode of the counters A, B, C and D according to the other configuration settings.
When CntPWM0 is enabled, the PWMA or PWMAB output value overrides the value set in bit 0 of RegPBOut in
the Port B peripheral. When CntPWM1 is enabled, the PWMC or PWMCD output value overrides the value set in
bit 1 of RegPBOut. The corresponding ports (0 and/or 1) of Port B must be set in digital mode and as output and
either open drain or not and pull up or not through a proper setting of the control registers of the Port B.
Counters in PWM mode count down or up, according to the CntXDownUp bit setting. No interrupts and events are
generated by the counters that are in PWM mode. Counters do count circularly: they restart at zero or at the
maximal value (either 0xFF when not cascaded or 0xFFFF when cascaded) when respectively an overflow or an
underflow condition occurs in the counting.
The internal PWM signals are low as long as the counter contents are higher than the PWM code values written in
the RegCntX registers. They are high when the counter contents are smaller or equal to these PWM code values.
In order to have glitch free outputs, the PWM outputs on PB(0) and PB(1) are sampled versions of these internal
PWM signals, therefore delayed by one counter clock cycle.
dow n counting
clock counter X
RegcntX_r
XX
32
10
32
10
32
10
RegCntX_w
XX
3
write RegCntX
CntXDow nUp
IrqX
CntXEnable
up counting
clock counter X
RegCntX_r
XX
0
1
23
01
230
12
3
RegCntX_w
XX
3
write RegCntX
CntXDow nUp
IrqX
CntXEnable
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