參數(shù)資料
型號： XE8000EV108
廠商： Semtech
文件頁數(shù)： 32/143頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8806/XE8807
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： XE88LC06AMI026
所含物品： 完全組裝的評估板
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
Semtech 2006
www.semtech.com
17-6
XE8806A/XE8807A
The external clock sources can be debounced or not by properly setting the PortA configuration registers.
Additionally, the external clock sources can be divided by two in the counter block, thus enabling higher external
clock frequencies, by setting the CntXExtDiv bits in the RegCntOn register.
Switching between an internal and an external clock source can only be performed while the counter is stopped.
The enabling or disabling of the external clock frequency division can only be performed while the counter using
this clock is stopped, or when this counter is running on an internal clock source.
17.8
Counter mode selection
Each counter can work in one of the following modes:
1) Counter, downcount & upcount
2) Captured counter, downcount & upcount (only counters A&B)
3) PWM, downcount & upcount
4) Captured PWM, downcount and upcount
The counters A and B or C and D can be cascaded or not. In cascaded mode, A and C are the LSB counters while
B and D are the MSB counters.
Table 17-12 shows the different operation modes of the counters A and B as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntADownUp or the bit
CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these
different modes is shown.
CascadeAB
CountPWM0
CapFunc(1:0)
Counter A
mode
Counter B
mode
IrqA
source
IrqB
source
PB(0)
function
0
00
Counter 8b
Downup: A
Counter 8b
Downup: B
Counter
A
Counter
B
PB(0)
1
0
00
Counter 16b AB
Downup: A
Counter
AB
-
PB(0)
0
1
00
PWM 8b
Downup: A
Counter 8b
Downup: B
-
Counter
B
PWM A
1
00
PWM 10 – 16b AB
Downup A
-
PWM AB
0
1x
or
x1
Captured
counter 8b
Downup: A
Captured
counter 8b
Downup: B
Capture
A
Capture
B
PB(0)
1
0
1x
or
x1
Captured counter 16b AB
Downup: A
Capture
AB
Capture
AB
PB(0)
0
1
1x
or
x1
Captured
PWM 8b
Downup: A
Captured
counter 8b
Downup: B
Capture
A
Capture
B
PWM A
1
1x
or
x1
Captured 10 – 16b PWM
(captured value on 16b)
Downup: A
Capture
AB
Capture
AB
PWM AB
Table 17-12: Operating modes of the counters A and B
Table 17-13 shows the different operation modes of the counters C and D as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntCDownUp or the bit
CntDDownUp). The mapping of the interrupt sources IrqC and IrqD and the PWM output on PB(1) in these
different modes is also shown.
The switching between different modes must be done while the concerned counters are stopped. While switching
capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode
change.
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