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| 型號： | XE8000EV108 |
| 廠商： | Semtech |
| 文件頁數(shù)： | 135/143頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XE8806/XE8807 |
| 標準包裝： | 1 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | XE88LC06AMI026 |
| 所含物品： | 完全組裝的評估板 |
| 產(chǎn)品目錄頁面： | 585 (CN2011-ZH PDF) |
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Semtech 2006
www.semtech.com
14-11
XE8806A/XE8807A
14.8.5
Reception interrupts
Only one interrupt line is dedicated to the RF receiver interface. The interrupt can be generated by three different
sources however. The bits RfifRxIrqEn[2:0] in RegRfifCmd3 allow the selection of the interrupt source(s) as
shown in Table 14-15. Possible interrupt sources are the detection of a message start, the shift of the first byte in
the FIFO after the FIFO was cleared and finally when the FIFO is full. The bits RfifRxIrqMem[2:0] in
RegRfifCmd3 flag which interrupt source was active since these bits were last cleared. The interrupt flags are
cleared by writing a 1. More than one interrupt source can be enabled at the same time.
RfifRxIrqEn[2:0]
RfifRxIrqMem[2:0]
Interrupt source
XX1
Start sequence detection
X1X
A new byte is written to FIFO
1XX
FIFO is full
Table 14-15. Reception interrupt source selection
The first interrupt allows easy synchronization to the message start. The second interrupt can be used if one wants
to download the message one byte at a time. The third interrupt can be used if one wants to download the
message 4 bytes at a time.
14.9
Transmission mode
The interface is configured in reception mode by setting the bit RfifEnTx (1 = enable) and clearing the bit RfifEnRx
(0 = disable reception) in the register RegRfifCmd3. When the transmission mode is switched off again, the
transmission will stop when the transmission of the byte in the shift register is completed.
The output data stream will be generated on the RFIF3 pin.
14.9.1
Transmission FIFO
Data to be transmitted are written to the FIFO by writing to the register RegRfifTx. These data are then loaded in
the shift register which sends the data bit by bit to the encoder (Figure 14-1). If the transmission FIFO is full, the bit
RfifTxFifoFull in RegRfifTxSta is set to 1. If the software continues to write data to the FIFO while it is full, the flag
RfifTxFifoOverrun will be set to 1 and the data will be lost. The RfifTxFifoOverrun flag is cleared by writing a 1 to
it. This clears the contents of the transmission FIFO at the same time. When the last data byte present in the FIFO
is loaded in the shift register, the flag RfifTxFifoEmpty is set to 1. If the software does not write new data to the
FIFO and the shift register finished shifting the last bit to the encoder, the bit RfifTxStopped is set to 1. The RFIF3
pin remains in the last encoded state.
The first bit sent is the bit RfifTx[0], the second bit is RfifTx[1] and so on.
14.9.2
Transmission interrupts
Only one interrupt source exists during the transmission: an interrupt can be generated at the moment the last byte
of the FIFO is transferred to the transmission shift register. It means that the FIFO is empty and has to be refilled
with data. The interrupt is enabled in the interrupt manager block.
14.9.3
Transmission encoding
The transmission encoder can be bypassed by clearing the bit RfifEnCod in register RegRfifCmd2. The bit stream
on the RFIF3 pin is then directly connected to the output of the shift register.
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