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參數(shù)資料
| 型號(hào)： | XE8000EV108 |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 140/143頁(yè) |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XE8806/XE8807 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | XE88LC06AMI026 |
| 所含物品： | 完全組裝的評(píng)估板 |
| 產(chǎn)品目錄頁(yè)面： | 585 (CN2011-ZH PDF) |
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Semtech 2006
www.semtech.com
14-16
XE8806A/XE8807A
14.12.1.2.1
XE1201A set-up
To set the XE1201A in reception mode, set the pin EN to 1 and the pin RXTX to 1. The data rate of the XE1201A
by default is 16kbit/s and the bit synchronizer is enabled by default. This means that the data registers of the
XE1201A can remain in the default settings shown in Table 14-20. The serial interface connections of Figure 14-8
are therefore not required.
Register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register A
0
1
0
Register B
0
Register C
0
1
0
1
0
1
0
1
0
Table 14-20. XE1201A default register set-up (see XE1201A datasheet for bit explanation)
14.12.1.2.2
RF interface set-up
Set-up the RF interface of the microcontroller circuit as a receiver (RfifEnRx = 1 and RfifEnTx = 0).
Assume that the RC clock frequency used in the microcontroller is 1.0 MHz. To select the correct baud rate of 16
kbit/s according to the equation in chapter 14.10, fine*coarse=1.0e06/(16*16e3)=3.9. This can be approximated at
4 (see specification in Table 14-19). This can be done by setting RfifBRCoarse = 01 and RfifBRFine = 0000.
The external bit synchronization clock is switched off by setting the bit RfifRxClock = 0.
The decoder is enabled and set to NRZ level decoding by setting RfifEnCod = 1 and RfifPCM = 000.
The start pattern detection is enabled by setting RfifEnStart = 11 and writing 11010111 to RfifRxSPat.
The start sequence detection interrupt is enabled by setting RfifRxIrqEn = 001.
The set-up of the interface is summarized in the Table 14-21.
Register
contents
RegRfifCmd1
00010000
RegRfifCmd2
11100000
RegRfifCmd3
00100010
RegRfifRxSPat
11010111
Table 14-21. RF interface set-up
14.12.1.2.3
Data reception
In order to handle the received data by interrupt, enable the RF interface reception interrupt in the interrupt handler
of the circuit.
Data received before the first start pattern detection after the enabling of the interface are not relevant since we are
not yet synchronized to the messages. Since the start detection interrupt has been enabled, nothing has to be
done until the interrupt occurs.
When the first interrupt occurs, we are synchronized to the messages. In order to read data in an efficient way, the
interrupt source is modified and set to “Rx FIFO full” by writing 100 to RfifRxIrqEn. Once this is done, we can wait
for the next interrupt to download the received message.
At each new interrupt, we can now read 4 bytes of the received message by reading the register RegRfifRx 4
consecutive times. The interrupt should be served before the next byte is received since otherwise data may be
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