參數(shù)資料
型號： XE8000EV108
廠商： Semtech
文件頁數(shù)： 61/143頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XE8806/XE8807
標準包裝： 1
類型： MCU
適用于相關產(chǎn)品： XE88LC06AMI026
所含物品： 完全組裝的評估板
產(chǎn)品目錄頁面： 585 (CN2011-ZH PDF)
Semtech 2006
www.semtech.com
4-2
XE8806A/XE8807A
4.1
Memory organisation
The XE8806A and XE8807A CPU are built with Harvard architecture. The Harvard architecture uses separate
instruction and data memories. The instruction bus and data bus are also separated. The advantage of such a
structure is that the CPU can fetch a new instruction and read/write data simultaneously. The circuit configuration is
shown in Figure 4-1. The CPU has its 16 internal registers. The instruction memory has a capacity of 8192 22-bit
instructions in the XE8806A and 4096 22-bit instructions in the XE8807A. The data memory space has 8 low power
registers, the peripheral register space and 512 bytes of RAM.
Figure 4-1. Memory mapping
The CPU internal registers are described in the CPU chapter. A short reference of the low power registers and
peripheral registers is given in 4.2.
4.2
Quick reference data memory register map
The data register map is given in the tables below. A more detailed description of the different registers is given in
the detailed description of the different peripherals.
The tables give the following information:
1.
The register name and register address
2.
The different bits in the register
3.
The access mode of the different bits (see Table 4-1 for code description)
4.
The reset source and reset value of the different bits
The reset source coding is given in Table 4-2. To get a full description of the reset sources, please refer to the
reset block chapter.
0h027F
RAM
capacity:
512 bytes
0h0080
0h1FFF
Instruction
memory
capacity:
XE8806A
8k x 22bit
XE8807A
4k x 22bit
CPU
in
te
rn
al
r
eg
iste
rs
a
stat
iph
ipl
i3h
i3l
i2h
i2l
i1h
i1l
i0h
i0l
r3
r2
r1
r0
Low power
data registers
0h0000
0h007F
Peripheral
registers
0h0008
Da
ta
mem
o
ry
dat
abus
ins
truct
ion
bus
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