參數(shù)資料
型號: W25Q16VSFIG
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 2M X 8 SPI BUS SERIAL EEPROM, PDSO16
封裝: 0.300 INCH, GREEN, PLASTIC, SOIC-16
文件頁數(shù): 40/60頁
文件大?。?/td> 1438K
代理商: W25Q16VSFIG
W25Q16V
Publication Release Date: October 7, 2009
- 45 -
Revision E
10.2.28 Continuous Read Mode Reset (FFh or FFFFh)
For Fast Read Dual/Quad I/O operations, “Continuous Read Mode” Bits (M7-0) are implemented to
further reduce instruction overhead. By setting the (M7-0) to “Ax” hex, the next Fast Read Dual/Quad
I/O operation does not require the BBh/EBh instruction code (See 10.2.12 Fast Read Dual I/O and
10.2.13 Fast Read Quad I/O for detail descriptions).
If the system controller is Reset during operation it will likely send a standard SPI instruction, such
as Read ID (9Fh) or Fast Read (0Bh), to the W25Q16. However, as with most SPI Serial Flash
memories, the W25Q16 does not have a hardware Reset pin, so if Continuous Read Mode bits are set
to “Ax” hex, the 25Q16 will not recognize any standard SPI instructions. To address this possibility, it is
recommended to issue a Continuous Read Mode Reset instruction as the first instruction after a system
Reset. Doing so will release the Continuous Read Mode from the “Ax” hex state and allow Standard SPI
instructions to be recognized. The Continuous Read Mode Reset instruction is shown in figure 29.
/CS
Mode 0
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
Mode 3
CLK
IO
0
IO
1
IO
2
IO
3
Mode Bit Reset
for Quad I/O
Mode Bit Reset
for Dual I/O
Don’t Care
FFh
/CS
Mode 0
Mode 3
00
11
22
33
44
55
66
77
88
99
10
11
12
13
14
15
Mode 0
Mode 3
CLK
IO
0
IO
1
IO
2
IO
3
Mode Bit Reset
for Quad I/O
Mode Bit Reset
for Dual I/O
Don’t Care
FFh
Figure 29. Continuous Read Mode Reset for Fast Read Dual/Quad I/O
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The
instruction is “FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are
needed to shift in instruction “FFFFh”.
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