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參數(shù)資料
| 型號： | W25Q16VSFIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 8 SPI BUS SERIAL EEPROM, PDSO16 |
| 封裝： | 0.300 INCH, GREEN, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 14/60頁 |
| 文件大小： | 1438K |
| 代理商： | W25Q16VSFIG |
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W25Q16V
Publication Release Date: October 7, 2009
- 21 -
Revision E
10.2.7 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction
(Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS
low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in
figure 7. The Status Register bits are shown in figure 3 and described earlier in this datasheet.
Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7, 5, 4, 3, 2 of Status
Register-1) and QE, SRP1(bits 9 and 8 of Status Register-2) can be written to. All other Status Register
bit locations are read-only and will not be affected by the Write Status Register instruction.
The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not
done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth
clock (compatible with the 25X series) the QE and SRP1 bits will be cleared to 0. After /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register
instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the
Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions
again. After the Write Register cycle has finished the Write Enable Latch (WEL) bit in the Status
Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (SEC, TB, BP2, BP1 and BP0) to be
set for protecting all, a portion, or none of the memory from erase and program instructions. Protected
areas become read-only (see Status Register Memory Protection table and description). The Write
Status Register instruction also allows the Status Register Protect bits (SRP0, SRP1) to be set. Those
bits are used in conjunction with the Write Protect (/WP) pin, Lock out or OTP features to disable writes
to the status register. Please refer to 10.1.6 for detailed descriptions regarding Status Register
protection methods. Factory default for all status Register bits are 0.
Figure 7. Write Status Register Instruction Sequence Diagram
相關PDF資料 |
PDF描述 |
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| W25Q32DWZPIP | 256K X 16 SPI BUS SERIAL EEPROM, 7.5 ns, PDSO8 |
| W25Q80VZPIG | 1M X 8 SPI BUS SERIAL EEPROM, DSO8 |
| W25X16AVDAIZ | 2M X 8 FLASH 2.7V PROM, PDIP8 |
| W25X40AVSSIG | 512K X 8 FLASH 2.7V PROM, PDSO8 |
| W25X80AVDAIZ | 1M X 8 FLASH 2.7V PROM, PDIP8 |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q16VSSIG | 功能描述:IC FLASH 16MBIT 80MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| W25Q16VZPIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q20BW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q20BWSNIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q20BWSNIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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