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參數(shù)資料
| 型號： | W25Q16VSFIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 2M X 8 SPI BUS SERIAL EEPROM, PDSO16 |
| 封裝： | 0.300 INCH, GREEN, PLASTIC, SOIC-16 |
| 文件頁數(shù)： | 31/60頁 |
| 文件大小： | 1438K |
| 代理商： | W25Q16VSFIG |
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W25Q16V
Publication Release Date: October 7, 2009
- 37 -
Revision E
10.2.20 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 20.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any
section of the array is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register
Memory Protection table).
Figure 20. Chip Erase Instruction Sequence Diagram
相關PDF資料 |
PDF描述 |
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| W25Q32DWZPIP | 256K X 16 SPI BUS SERIAL EEPROM, 7.5 ns, PDSO8 |
| W25Q80VZPIG | 1M X 8 SPI BUS SERIAL EEPROM, DSO8 |
| W25X16AVDAIZ | 2M X 8 FLASH 2.7V PROM, PDIP8 |
| W25X40AVSSIG | 512K X 8 FLASH 2.7V PROM, PDSO8 |
| W25X80AVDAIZ | 1M X 8 FLASH 2.7V PROM, PDIP8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q16VSSIG | 功能描述:IC FLASH 16MBIT 80MHZ 8SOIC RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| W25Q16VZPIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q20BW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q20BWSNIG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q20BWSNIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
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