參數(shù)資料
型號(hào): VG4632321AQ-7
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 524,288x32x2-Bit CMOS Synchronous Graphic RAM
中文描述: 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 8/81頁
文件大?。?/td> 1965K
代理商: VG4632321AQ-7
Document:
Rev.1
Page 8
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
Read to Write interval (Burst Length
°
4, CAS Latency = 3)
DQM
DOUT A
0
DQ’s
DINB
0
DINB
1
DINB
2
: “H” or “L”
Must be Hi-Z before
the Write Command
CLK
COMMAND
NOP
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
Read to Write interval (Burst Length
°
4, CAS Latency = 1, 2)
DQM
DIN A
0
DIN A
1
DIN A
2
DIN A
3
: “H” or “L”
Must be Hi-Z before
the Write Command
DIN A
0
DIN A
1
DIN A
2
DIN A
3
CAS Iatency = 1
t
CK1
,DQ’s
CAS Iatency = 2
t
CK2
,DQ’s
CLK
COMMAND
NOP
NOP
NOP
WRITE B
NOP
NOP
NOP
Read to Write interval (Burst Length
°
4, CAS Latency = 1, 2)
DQM
DIN B
0
DIN B
1
DINB
2
DIN B
3
: “H” or “L”
Must be Hi-Z before
the Write Command
DIN B
0
DIN B
1
DIN B
2
DIN B
3
CAS Iatency = 1
t
CK1
,DQ’s
CAS Iatency = 2
t
CK2
,DQ’s
READ A
DOUT A
0
NOP
A read burst without auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS latency.
1 Clk Interval
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