參數(shù)資料
型號(hào): VG4632321AQ-7
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 524,288x32x2-Bit CMOS Synchronous Graphic RAM
中文描述: 1M X 32 SYNCHRONOUS GRAPHICS RAM, 6 ns, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 5/81頁(yè)
文件大?。?/td> 1965K
代理商: VG4632321AQ-7
Document:
Rev.1
Page 5
VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2
shows the truth table for the operation commands.
Table 2. Truth Table (Note(1), (2))
Note: 1. V = Valid X = Don’t Care L = Low level H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not entry in the burst operation.
When this command assert in the burst cycle, device state is clock suspend mode.
7. DQM0-3
Command
State
CKEn-1
CKEnDQM
(7)
BS
A8
A0-7
A9,
A10
CS
RAS CAS
WE
DSF
BankActivate & Masked Write Disable
Idle
(3)
H
X
X
V
V
V
L
L
H
H
L
BankActivate & Masked Write Enable
Idle
(3)
H
X
X
V
V
V
L
L
H
H
H
BankPrecharge
Any
H
X
X
V
L
X
L
L
H
L
L
PrechargeAll
Any
H
X
X
X
H
X
L
L
H
L
L
Write
Active
(3)
H
X
X
V
L
V
L
H
L
L
L
Block Write Command
Active
(3)
H
X
X
V
L
V
L
H
L
L
H
Write and AutoPrecharge
Active
(3)
H
X
X
V
H
V
L
H
L
L
L
Block Write and AutoPrecharge
Active
(3)
H
X
X
V
H
V
L
H
L
L
H
Read
Active
(3)
H
X
X
V
L
V
L
H
L
H
L
Read and AutoPrecharge
Active
(3)
H
X
X
V
H
V
L
H
L
H
L
Mode Register Set
Idle
H
X
X
V
L
V
L
L
L
L
L
Special Mode Register Set
Idle
(5)
H
X
X
X
X
V
L
L
L
L
H
No-Operation
Any
H
X
X
X
X
X
L
H
H
H
X
Burst Stop
Active
(4)
H
X
X
X
X
X
L
H
H
L
L
Device Deselect
Any
H
X
X
X
X
X
H
X
X
X
X
AutoRefresh
Idle
H
H
X
X
X
X
L
L
L
H
L
SelfRefresh Entry
Idle
H
L
X
X
X
X
L
L
L
H
L
SelfRefresh Exit
Idle
(SelfRefresh)
L
H
X
X
X
X
H
X
X
X
X
L
H
H
H
X
Clock Suspend Mode Entry
Active
H
L
X
X
X
X
X
X
X
X
X
Power Down Mode Entry
Any
(6)
H
L
X
X
X
X
H
X
X
X
X
L
H
H
H
L
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
X
Power Down Mode Exit
Any
(Power-
Down)
L
H
X
X
X
X
H
X
X
X
X
L
H
H
H
L
Data Write/Output Enable
Active
H
X
L
X
X
X
X
X
X
X
X
Data Write/Output Disable
Active
H
X
H
X
X
X
X
X
X
X
X
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